简单的 VHDL 时钟计数器仿真混淆

Question

我目前对我的简单计数器有点困惑。 实现如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity simple_counter is
    port( 
        DOUT : out std_logic_vector(3 downto 0);
        CE : in std_logic;
        CLK : in std_logic;
        RSTN : in std_logic
    );
end simple_counter;

architecture behavioral of simple_counter is
    signal temp : unsigned(3 downto 0);

begin   

    process(CLK)
    begin
        if RSTN = '0' then
            temp <= (others => '0');
        elsif(rising_edge(CLK)) then
            if CE = '1' then
                if std_logic_vector(temp) = (temp'range => '1') then
                    temp <= (others => '0');
                else
                    temp <= temp + 1;
                end if;
            end if;
        end if;
    end process;

    DOUT <= std_logic_vector(temp);

end behavioral;

我使用以下测试台进行模拟：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;

use work.tools_pkg.all;

library work;

--! @class  tools_tb
--! @brief  Test bench for the tools_tb design
entity counter_tb is
  generic (
    VOID : integer := 0);
  port (
    void_i : in std_logic);
end entity counter_tb;

--! @brief
--! @details
architecture sim of counter_tb is

    -- Clock period definitions
    -- Clock, reset and baud rate definitions
    constant CLK_FREQ   : integer   := 100_000_000;
    constant clk_period : time      := (1.0 / real(CLK_FREQ)) * (1 sec);
    signal end_sim          : boolean := false;

    signal rstn             : std_logic;
    signal clk              : std_logic;
    signal s_en             : std_logic := '0';

    ------------------------------------------------------------------------------
    -- DUT signals
    ------------------------------------------------------------------------------

    signal s_dout        : std_logic_vector(3 downto 0) := (others => '0');
    signal s_ce          : std_logic := '0';

begin  -- architecture 


    fifo : entity work.simple_counter
    port map (
        DOUT => s_dout,
        CE  => s_ce,
        RSTN => rstn,
        CLK => clk
    );


    -- Clock process definitions (clock with 50% duty cycle is generated here).
    clk_process : process
    begin
        if end_sim = false then
            clk <= '1';
            wait for clk_period/2;
            clk <= '0';
            wait for clk_period/2;
        else
            wait;
        end if;
    end process;

    -- Stimulus process
    stim_proc: process
    begin
        -- startup and wait for some time
        rstn <= '0';
        wait for clk_period;
        rstn <= '1';
        wait for clk_period;
        wait for clk_period;
        wait for clk_period;

        s_ce <= '1';

        wait;
    end process;

end architecture sim;

我很困惑为什么当我设置CE <= '1 时计数器会立即增加 （见附件模拟）。 由于计数器是在同步过程中实现的，所以它从'0'增加到'1'不应该需要一个时钟周期吗？

非常感谢！

Answer 1

您很可能在s_ce 和clk 之间存在竞争条件。如果您将在clk 的上升沿生成s_ce，那么您应该会看到该计数器正常工作。

我不知道这个模拟器，但要检查比赛，你可以在计数器更改 0->1 时扩展 deltas