在VHDL中进行波形仿真时忽略时钟输入？

Question

我是硬件描述语言理论和 VHDL 的新手。我需要用 VHDL 设计一个 2421 计数器。我使用 T 触发器构建了一个同步二进制递增计数器，并通过有条件地激活预设和清除来对其进行修改以生成最后 2 个所需的计数 8 和 9。当我尝试波形仿真时，时钟输入被忽略。无法弄清楚问题是什么。代码如下：

library ieee;  
use ieee.std_logic_1164.all;  
entity count2421 is    
port(clock:in std_logic;qq:buffer std_logic_vector(3 downto 0));  
end count2421;  
architecture arch of count2421 is  
component t_ff is  
port(clock,clear,preset,t:in std_logic;q:buffer std_logic);  
end component;  
signal p1,p2,p,t,u,a,b:std_logic;  
begin  
    t<='1';  
    u<='0';  
    qq(0)<='0';  
    qq(1)<='0';  
    qq(2)<='0';  
    qq(3)<='0';  
    process(clock) begin  
        if(clock'event and clock='0') then  
            p1<=(not qq(3)) and qq(2) and qq(1) and qq(0);  
            p2<=qq(3) and qq(2) and qq(1) and (not qq(0));  
            p<=p1 or p2;  
            a<=qq(3) and qq(2);  
            b<=a and qq(1);  
        end if;  
    end process;  
    stage0:t_ff port map(clock,u,p,t,qq(0));  
    stage1:t_ff port map(clock,u,p,qq(0),qq(1));  
    stage2:t_ff port map(clock,u,p,a,qq(2));  
    stage3:t_ff port map(clock,p1,p2,b,qq(3));  
end arch;  

这里是 T 触发器代码：

library ieee;  
  use ieee.std_logic_1164.all;  
  entity t_ff is  
    port(clock,clear,preset,t:in std_logic;q:buffer std_logic);  
  end t_ff;  
  architecture arch of t_ff is  
signal temp:std_logic;  
begin  
    temp<=q;  
    process(clock)  
    begin  
        if(clock'event and clock='0') then  
            if(clear='1') then   
                q<='0';  
            elsif(preset='1') then  
                q<='1';  
            elsif(t='1') then  
                q<=not q;  
            end if;  
        end if;  
    end process;  
end arch;

Answer 1

缓冲端口qq有两个驱动。 在担心其他任何事情之前先解决这个问题。