异步复位实例:
1 module async_rst ( 2 input din, 3 input clk, 4 input rst_n, 5 6 output reg dout 7 ); 8 9 always @ (posedge clk or negedge rst_n) 10 begin 11 if (!rst_n) 12 dout <= 1'b0; 13 else 14 dout <= din; 15 end 16 17 endmodule
1 module async_rst ( 2 input din, 3 input clk, 4 input rst_n, 5 6 output reg dout 7 ); 8 9 always @ (posedge clk or negedge rst_n) 10 begin 11 if (!rst_n) 12 dout <= 1'b0; 13 else 14 dout <= din; 15 end 16 17 endmodule
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