--------------------- 本文来自 爬行的娲牛 的CSDN 博客 ，全文地址请点击：https://blog.csdn.net/frank_wff/article/details/43226507?utm_source=copy
module reset_best(clk,asyn_reset,syn_reset);
input clk;
input asyn_reset;
output syn_reset;
reg rst_s1;
reg rst_s2;
[email protected](posedge clk or negedge asyn_reset)
begin
if(!asyn_reset) begin
rst_s1<=1'b0;
rst_s2<=1'b0;
end
else begin
rst_s1<=1'b1;
rst_s2<=rst_s1;
end
end
assign syn_reset=rst_s2;
endmodule