10. Logic Synthesis
10.1. three steps: translate, logic optimize, gate map
10.2. design objects: clock, reference, cell, pin, net, etc. WHO IS WHO
10.3. timing
construction time: data stable time before the clock rise;
holding time: data stable time after the clock rise.
10.4. design compiler workflow
10.4.1. mode
tcl is recommended.
10.4.2. read
read command
analyze & elaborate commands
read vs. a&e
11. Libraries
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