VHDL 上的多路复用器

Question

我尝试创建多路复用器：

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY multiplekser IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
U : IN STD_LOGIC_VECTOR(2 downto 0);
V : IN STD_LOGIC_VECTOR(2 downto 0);
W : IN STD_LOGIC_VECTOR(2 downto 0);
X : IN STD_LOGIC_VECTOR(2 downto 0);
Y : IN STD_LOGIC_VECTOR(2 downto 0);
S : IN STD_LOGIC_VECTOR(2 downto 0);
CS : IN STD_LOGIC;
M : OUT STD_LOGIC_VECTOR(2 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

END multiplekser;


--  Architecture Body

ARCHITECTURE multiplekser_architecture OF multiplekser IS


BEGIN
    PROCESS(CS)
    BEGIN
    if (CS = '1') then
        with S select
            M<=U when "000",
                V when "001",
                W when "010",
                X when "011",
                Y when others;
    else 
        M<="ZZZ";
    end if;
    END PROCESS;
END multiplekser_architecture;

但出现了一些错误：

我是在 Quartus II 64 位上完成的。这是我的框图：

CS 为使能信号。当 CS 为 0 时，M(output) 必须为高阻抗。

Answer 1

您正在使用并发语句，其中需要顺序语句。

您应该使用一个 case 语句或一组 if 语句。例如：

architecture multiplekser_architecture of multiplekser is
begin
    process(cs, s, u, v, w, x, y)
    begin
        if cs = '1' then
            case S is
                when "000"  => m <= u;
                when "001"  => m <= v;
                when "010"  => m <= w;
                when "011"  => m <= x;
                when others => m <= y;
            end case;
        else
            m <= "ZZZ";
        end if;
    end process;
end architecture;