【发布时间】：2018-12-26 10:29:18
【问题描述】：
我正在尝试使用 VHDL 查找包含 19 个值的“数组”的最小值。这 19 个值由 J0 到 J18 表示，并用作我的 Find_min_v3 模块的输入。
下面的结构（在图片中）我用来比较 2 个输入，输出存储在 REG 中。无数结构的使用导致通知
“[网表 29-101] 网表‘模块’不适合平面规划，因为单元视图‘模块’包含大量原语。如果您想进行布局规划，请考虑在综合中启用层次结构。”
我有两个问题：
1.为什么它包含许多导致布局规划不理想的原语
2.如何优化连接的无数结构以找到数组的最小值？或者你有其他方法来找到最小值吗？
这是我的代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Find_min_v3 is
Port ( i_clk : in STD_LOGIC;
reset : in STD_LOGIC;
EN_RUNNING : in STD_LOGIC;
J0 : in STD_LOGIC_VECTOR (11 downto 0);
J1 : in STD_LOGIC_VECTOR (11 downto 0);
J2 : in STD_LOGIC_VECTOR (11 downto 0);
J3 : in STD_LOGIC_VECTOR (11 downto 0);
J4 : in STD_LOGIC_VECTOR (11 downto 0);
J5 : in STD_LOGIC_VECTOR (11 downto 0);
J6 : in STD_LOGIC_VECTOR (11 downto 0);
J7 : in STD_LOGIC_VECTOR (11 downto 0);
J8 : in STD_LOGIC_VECTOR (11 downto 0);
J9 : in STD_LOGIC_VECTOR (11 downto 0);
J10 : in STD_LOGIC_VECTOR (11 downto 0);
J11 : in STD_LOGIC_VECTOR (11 downto 0);
J12 : in STD_LOGIC_VECTOR (11 downto 0);
J13 : in STD_LOGIC_VECTOR (11 downto 0);
J14 : in STD_LOGIC_VECTOR (11 downto 0);
J15 : in STD_LOGIC_VECTOR (11 downto 0);
J16 : in STD_LOGIC_VECTOR (11 downto 0);
J17 : in STD_LOGIC_VECTOR (11 downto 0);
J18 : in STD_LOGIC_VECTOR (11 downto 0);
J_Min_out : OUT STD_LOGIC_VECTOR (11 downto 0)
);
end Find_min_v3;
architecture Behavioral of Find_min_v3 is
TYPE J_type IS ARRAY (0 to 18) OF SIGNED(11 downto 0) ;
SIGNAl r_J : J_type;
SIGNAl out_min_stage1_0 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_1 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_2 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_3 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_4 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_5 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_6 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_7 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_8 : SIGNED (11 downto 0);
SIGNAl out_min_stage1_9 : SIGNED (11 downto 0);
SIGNAl out_min_stage2_0 : SIGNED (11 downto 0);
SIGNAl out_min_stage2_1 : SIGNED (11 downto 0);
SIGNAl out_min_stage2_2 : SIGNED (11 downto 0);
SIGNAl out_min_stage2_3 : SIGNED (11 downto 0);
SIGNAl out_min_stage2_4 : SIGNED (11 downto 0);
SIGNAl out_min_stage3_0 : SIGNED (11 downto 0);
SIGNAl out_min_stage3_1 : SIGNED (11 downto 0);
SIGNAl out_min_stage3_2 : SIGNED (11 downto 0);
SIGNAl out_min_stage4_0 : SIGNED (11 downto 0);
SIGNAl out_min_stage4_1 : SIGNED (11 downto 0);
SIGNAl out_min_stage5_0 : SIGNED (11 downto 0);
BEGIN
r_J(0) <= signed(J0) WHEN EN_RUNNING ='1';
r_J(1) <= signed(J1) WHEN EN_RUNNING ='1';
r_J(2) <=signed(J2) WHEN EN_RUNNING ='1';
r_J(3) <=signed(J3) WHEN EN_RUNNING ='1';
r_J(4) <=signed(J4) WHEN EN_RUNNING ='1';
r_J(5) <=signed(J5) WHEN EN_RUNNING ='1';
r_J(6) <=signed(J6) WHEN EN_RUNNING ='1';
r_J(7) <=signed(J7) WHEN EN_RUNNING ='1';
r_J(8) <=signed(J8) WHEN EN_RUNNING ='1';
r_J(9) <=signed(J9) WHEN EN_RUNNING ='1';
r_J(10) <=signed(J10) WHEN EN_RUNNING ='1';
r_J(11) <=signed(J11) WHEN EN_RUNNING ='1';
r_J(12) <=signed(J12) WHEN EN_RUNNING ='1';
r_J(13) <=signed(J13) WHEN EN_RUNNING ='1';
r_J(14) <=signed(J14) WHEN EN_RUNNING ='1';
r_J(15) <=signed(J15) WHEN EN_RUNNING ='1';
r_J(16) <=signed(J16) WHEN EN_RUNNING ='1';
r_J(17) <=signed(J17) WHEN EN_RUNNING ='1';
r_J(18) <=signed(J18) WHEN EN_RUNNING ='1';
-------stage1
STAGGE1_0: PROCESS (i_clk,reset)
BEGIN
IF (RISING_EDGE(i_clk)) THEN
IF (reset ='0') THEN
--out_ind_stage1_0 <= (others => '0');
out_min_stage1_0 <= (others => '0');
out_min_stage1_0 <= (others => '0');
out_min_stage1_1 <= (others => '0');
out_min_stage1_2 <= (others => '0');
out_min_stage1_3 <= (others => '0');
out_min_stage1_4 <= (others => '0');
out_min_stage1_5 <= (others => '0');
out_min_stage1_6 <= (others => '0');
out_min_stage1_7 <= (others => '0');
out_min_stage1_8 <= (others => '0');
out_min_stage1_9 <= (others => '0');
out_min_stage2_0 <= (others => '0');
out_min_stage2_1 <= (others => '0');
out_min_stage2_2 <= (others => '0');
out_min_stage2_3 <= (others => '0');
out_min_stage2_4 <= (others => '0');
out_min_stage3_0 <= (others => '0');
out_min_stage3_1 <= (others => '0');
out_min_stage3_2 <= (others => '0');
out_min_stage4_0 <= (others => '0');
out_min_stage4_1 <= (others => '0');
out_min_stage5_0 <= (others => '0');
ELSE
IF (r_J(1)>r_J(0)) THEN
out_min_stage1_0 <= r_J(0);
ELSE
out_min_stage1_0 <= r_J(1);
END IF;
IF (r_J(3)>r_J(2)) THEN
out_min_stage1_1 <= r_J(2);
ELSE
out_min_stage1_1 <= r_J(3);
END IF;
IF (r_J(5)>r_J(4)) THEN
out_min_stage1_2 <= r_J(4);
ELSE
out_min_stage1_2 <= r_J(5);
END IF;
IF (r_J(7)>r_J(6)) THEN
out_min_stage1_3 <= r_J(6);
ELSE
out_min_stage1_3 <= r_J(7);
END IF;
IF (r_J(9)>r_J(8)) THEN
out_min_stage1_4 <= r_J(8);
ELSE
out_min_stage1_4 <= r_J(9);
END IF;
IF (r_J(11)>r_J(10)) THEN
out_min_stage1_5 <= r_J(10);
ELSE
out_min_stage1_5 <= r_J(11);
END IF;
IF (r_J(13)>r_J(12)) THEN
out_min_stage1_6 <= r_J(12);
ELSE
out_min_stage1_6 <= r_J(13);
END IF;
IF (r_J(15)>r_J(14)) THEN
out_min_stage1_7 <= r_J(14);
ELSE
out_min_stage1_7 <= (r_J(15));
END IF;
IF (r_J(17)>r_J(16)) THEN
out_min_stage1_8 <= r_J(16);
ELSE
out_min_stage1_8 <= r_J(17);
END IF;
out_min_stage1_9 <= r_J(18);
---------
IF (out_min_stage1_0)> out_min_stage1_1 THEN
out_min_stage2_0 <= out_min_stage1_1;
ELSE
out_min_stage2_0 <= out_min_stage1_0;
END IF;
IF (out_min_stage1_2)>(out_min_stage1_3) THEN
out_min_stage2_1 <= (out_min_stage1_3);
ELSE
out_min_stage2_1 <= (out_min_stage1_2);
END IF;
IF (out_min_stage1_4)>out_min_stage1_5 THEN
out_min_stage2_2 <= (out_min_stage1_5);
ELSE
out_min_stage2_2 <= (out_min_stage1_4);
END IF;
IF (out_min_stage1_6)>(out_min_stage1_7) THEN
out_min_stage2_3 <= (out_min_stage1_7);
ELSE
out_min_stage2_3 <= (out_min_stage1_6);
END IF;
IF (out_min_stage1_8)>out_min_stage1_9 THEN
out_min_stage2_4 <= (out_min_stage1_9);
ELSE
out_min_stage2_4 <= (out_min_stage1_8);
END IF;
---------STAGE3
IF (out_min_stage2_0)>out_min_stage2_1 THEN
out_min_stage3_0 <= (out_min_stage2_1);
ELSE
out_min_stage3_0 <= (out_min_stage2_0);
END IF;
IF (out_min_stage2_2)>(out_min_stage2_3) THEN
out_min_stage3_1 <= (out_min_stage2_3);
ELSE
out_min_stage3_1 <= (out_min_stage2_2);
END IF;
out_min_stage3_2 <= (out_min_stage2_4);
-------------STAGE4
IF (out_min_stage3_1)>out_min_stage3_0 THEN
out_min_stage4_0 <= (out_min_stage3_0);
ELSE
out_min_stage4_0 <= (out_min_stage3_1);
END IF;
out_min_stage4_1 <= (out_min_stage3_2);
-------------STAGE5
IF (out_min_stage4_0)>(out_min_stage4_1)THEN
out_min_stage5_0 <= (out_min_stage4_1);
ELSE
out_min_stage5_0 <= (out_min_stage4_0);
END IF;
J_Min_out <= STD_LOGIC_VECTOR(out_min_stage5_0);
END IF;
END IF;
END PROCESS;
end Behavioral;
【问题讨论】：
-
您能分享您的源代码和资源（例如 lut 和 bram）使用报告吗？
-
如果你的实现是基于一个排序网络来寻找最小值，那么所需的资源就会随着输入的数量和每个输入的大小而爆炸式增长。每个 64 位的 64 个输入向量可以填满当前可用的最大 FPGA！您应该一次寻找顺序或 n-out-of-m 输入的解决方案以节省资源。
-
@Paebbes。我明白了，但是我在原理图中添加了模块，以便输入的数量和每个输入的大小在 FPGA 中被视为 Signals,REG,....。我将在下面显示代码，真的希望你能帮助我
-
@delirium 我将在下面分享代码
-
首先，您确实使用了比您拥有的更多的 I/O 资源。正如@Paebbels 评论的那样，您应该调整您的解决方案（例如，序列化您的输入）以节省资源。
标签： vhdl