Verilog代码中未连接节点警告的原因答案

【问题标题】：Cause of unconnected node warnings in verilog codeVerilog代码中未连接节点警告的原因
【发布时间】：2018-08-08 20:54:13
【问题描述】：

我正在编写执行梯形积分方法的代码。该代码具有 FPGA 时钟（我使用的是 Mimas Spartan 6）、SIGNAL（积分中要考虑的新点）、x（点之间的间隔）和 SUM（过去输入积分的结果, 输出为 OUT。由于梯形法必须有两个输入，所以有两个寄存器 yregone 和 yregtwo，所以将 SIGNAL 设置为 yregone，将 yregtwo 设置为旧的 yregone（过去的 SIGNAL）。这两个是相加，然后位移位，使其除以 2，乘以 x，然后加上 SUM（OUT 映射到板上的 SUM）。

代码会根据给出的警告进行编译。我在其他地方读到过警告可以被忽略。尽管出现了错误，但代码还是编译了，所以我尝试将代码下载到板上，它说配置失败。因此，我假设警告必须指出代码中必须修复的一些错误。怎么了？

代码

module trapverilog(
    input CLK,
     input signed [7:0] SIGNAL,
     input [7:0] x,
     input signed [20:0] SUM, // OUT pins are mapped to SUM pins on board
     output reg OUT1,
     output reg OUT2,
     output reg OUT3,
     output reg OUT4,
     output reg OUT5,
     output reg OUT6,
     output reg OUT7,
     output reg OUT8,
     output reg OUT9,
     output reg OUT10,
     output reg OUT11,
     output reg OUT12,
     output reg OUT13,
     output reg OUT14,
     output reg OUT15,
     output reg OUT16,
     output reg OUT17,
     output reg OUT18,
     output reg OUT19,
     output reg OUT20
    );

reg signed [7:0] yregone;
reg signed [7:0] yregtwo;
reg signed [20:0] innerSumOutput;
reg signed [20:0] innerSum;

function [20:0] multiply;
    input signed [7:0] a;
    input signed [7:0] b;
    reg [15:0] a1, a2, a3, a4, a5, a6, a7, a8;
    begin
        a1 = (b[0]==1'b1) ? {8'b00000000, a} : 16'b0000000000000000;
        a2 = (b[1]==1'b1) ? {7'b0000000, a, 1'b0} : 16'b0000000000000000;
        a3 = (b[2]==1'b1) ? {6'b000000, a, 2'b00} : 16'b0000000000000000;
        a4 = (b[3]==1'b1) ? {5'b00000, a, 3'b000} : 16'b0000000000000000;
        a5 = (b[4]==1'b1) ? {4'b0000, a, 4'b0000} : 16'b0000000000000000;
        a6 = (b[5]==1'b1) ? {3'b000, a, 5'b00000} : 16'b0000000000000000;
        a7 = (b[6]==1'b1) ? {2'b00, a, 6'b000000} : 16'b0000000000000000;
        a8 = (b[7]==1'b1) ? {1'b0, a, 7'b0000000} : 16'b0000000000000000;
        multiply = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
    end
endfunction

always @(posedge CLK)
begin
    yregtwo <= yregone;
    yregone <= SIGNAL;

    if (yregone != 0)
    begin
        innerSum <= multiply((yregone + yregtwo), x); // treats x as plain h, change if treated as h/2 // multiply defined by function shift-adds
        innerSumOutput <= (innerSum <<< 1) + SUM; // <<< is signed one bit shift which = /2
        OUT20 <= innerSumOutput[20];
        OUT1 <= innerSumOutput[1]; // OUT is two's complement
        OUT2 <= innerSumOutput[2];
        OUT3 <= innerSumOutput[3];
        OUT4 <= innerSumOutput[4];
        OUT5 <= innerSumOutput[5];
        OUT6 <= innerSumOutput[6];
        OUT7 <= innerSumOutput[7];
        OUT8 <= innerSumOutput[8];
        OUT9 <= innerSumOutput[9];
        OUT10 <= innerSumOutput[10];
        OUT11 <= innerSumOutput[11];
        OUT12 <= innerSumOutput[12];
        OUT13 <= innerSumOutput[13];
        OUT14 <= innerSumOutput[14];
        OUT15 <= innerSumOutput[15];
        OUT16 <= innerSumOutput[16];
        OUT17 <= innerSumOutput[17];
        OUT18 <= innerSumOutput[18];
        OUT19 <= innerSumOutput[19];
    end
end

endmodule

UCF

NET "CLK" LOC = P126;
NET "SIGNAL[0]" LOC = P35 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[1]" LOC = P34 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[2]" LOC = P33 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[3]" LOC = P32 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[4]" LOC = P30 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[5]" LOC = P29 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[6]" LOC = P27 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[7]" LOC = P26 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[0]" LOC = P24 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[1]" LOC = P23 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[2]" LOC = P22 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[3]" LOC = P21 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[4]" LOC = P17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[5]" LOC = P16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[6]" LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[7]" LOC = P14 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[0]" LOC = P12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[1]" LOC = P11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[2]" LOC = P10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[3]" LOC = P9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[4]" LOC = P8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[5]" LOC = P7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[6]" LOC = P6 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[7]" LOC = P5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[8]" LOC = P2 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[9]" LOC = P1 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[10]" LOC = P142 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[11]" LOC = P141 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[12]" LOC = P140 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[13]" LOC = P139 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[14]" LOC = P138 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[15]" LOC = P137 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[16]" LOC = P134 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[17]" LOC = P133 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[18]" LOC = P132 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[19]" LOC = P131 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[20]" LOC = P43 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT1" LOC = P44 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT2" LOC = P45 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT3" LOC = P46 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT4" LOC = P47 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT5" LOC = P48 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; 
NET "OUT6" LOC = P50 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT7" LOC = P51 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT8" LOC = P55 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT9" LOC = P56 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; 
NET "OUT10" LOC = P74 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT11" LOC = P75 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT12" LOC = P78 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT13" LOC = P79 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT14" LOC = P80 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT15" LOC = P81 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT16" LOC = P82 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT17" LOC = P83 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT18" LOC = P84 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT19" LOC = P85 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT20" LOC = P87 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

警告

WARNING:Xst:2677 - Node <innerSum_20> of sequential type is unconnected in block <trapverilog>.
WARNING:Xst:2677 - Node <innerSumOutput_0> of sequential type is unconnected in block <trapverilog>.
WARNING:Xst:2677 - Node <innerSum_20> of sequential type is unconnected in block <trapverilog>.
WARNING:Xst:2677 - Node <innerSumOutput_0> of sequential type is unconnected in block <trapverilog>.
WARNING:Xst:1710 - FF/Latch <innerSum_19> (without init value) has a constant value of 0 in block <trapverilog>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <innerSum_16> (without init value) has a constant value of 0 in block <trapverilog>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <innerSum_17> (without init value) has a constant value of 0 in block <trapverilog>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <innerSum_18> (without init value) has a constant value of 0 in block <trapverilog>. This FF/Latch will be trimmed during the optimization process.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
WARNING:Par:288 - The signal SUM<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

【问题讨论】：

我看到 PAR 由于错误/警告而失败，但我从未见过下载因为错误/警告而失败。检查： 1/ 如果您的 PAR 和 Bitgen 运行没有错误。 2/ 如果您发送的文件类型正确。 3/ 如果您已针对正确的 Xilinx 器件进行编译。（还要检查足迹！）
@Oldfart 2) 和 3) 很好。 1) 是什么意思？
您在运行 PAR、Bitgen 或任何其他综合后赛灵思工具时是否遇到错误？您还有其他可以下载 的简单设计吗？只是为了检查没有硬件错误。
@Oldfart 我过去测试过的另一个简单设计无法下载。所以......显然还有其他问题。我给 ISE 的电路板类型是正确的，我不知道可能有什么问题。
这至少应该让您朝着正确的方向前进，检查电缆、连接器、电源等。我无能为力帮助您。祝你好运！

标签： configuration verilog fpga compiler-warnings spartan

【解决方案1】：

您需要了解这些工具给您的警告，而不仅仅是忽略它们。看起来您的设计中有很多未连接的信号和具有恒定值的 FF/锁存器——这可能意味着即使您设法下载它，它也不会做您希望它做的事情。最后一个 PAR 警告表示 DRC 错误，这可能是您的问题的根源，因为 Bitgen 不确定如何处理您的无负载信号。尝试清理警告（或至少确保您了解所有警告并知道哪些是可以安全忽略的），然后再试一次。

您的设计是否可以模拟？如果答案是“什么模拟？”我强烈建议您在综合和 PAR 之前确保您可以对您的设计进行简单的模拟。

【讨论】：