【发布时间】：2020-05-07 00:17:02
【问题描述】：
我正在做一个项目，但我没弄明白。我只是看不出我做错了什么。任何建议都非常感谢。该项目采用 VHDL 语言，这是 Spartan 3e 入门板上的大约 4 位密码锁。这是我第一次用 VHDL 做项目。
我收到了一些警告：
WARNING:Xst:2677 - Node <cur_val1_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <cur_val1_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <cur_val1_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <cur_val1_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <next_val1_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <next_val1_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <next_val1_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <next_val1_3> of sequential type is unconnected in block <top>.
WARNING:Xst:737 - Found 4-bit latch for signal <next_val2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <next_val3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <next_val4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <next_state>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
这是我的源代码：
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
USE IEEE.std_logic_unsigned.all;
entity top is
Port (
PB1:in STD_LOGIC;
PB2:in STD_LOGIC;
PB3:in STD_LOGIC;
PB4:in STD_LOGIC;
clock:in STD_LOGIC;
unlock1: out STD_LOGIC_VECTOR (3 downto 0);
unlock2: out STD_LOGIC_VECTOR (3 downto 0);
unlock3: out STD_LOGIC_VECTOR (3 downto 0);
unlock4: out STD_LOGIC_VECTOR (3 downto 0);
LED1:out STD_LOGIC_VECTOR (3 downto 0); --LED 0 - 3
LED2:out STD_LOGIC_VECTOR (3 downto 0) --LED 4 - 7
);
end top;
architecture Behavioral of top is
subtype val_type is integer range 0 to 9;
signal cur_val1, cur_val2, cur_val3, cur_val4 : val_type;
signal reset_state, save_state : val_type;
signal next_val1, next_val2, next_val3, next_val4 : val_type;
signal save_type1, save_type2, save_type3, save_type4: val_type;
signal unlock_type1, unlock_type2, unlock_type3, unlock_type4: val_type;
type state_type is (s0,s1,s2,s3);
signal cur_state, next_state : state_type;
begin
VAL_PROC: process (clock)
begin
if rising_edge(clock) then
cur_val1 <= next_val1;
cur_val2 <= next_val2;
cur_val3 <= next_val3;
cur_val4 <= next_val4;
end if;
end process;
STATE_PROC: process(clock,PB4)
begin
if(PB4='1') then
cur_state <= s0;
elsif rising_edge(clock) then
cur_state <= next_state;
end if;
end process;
NEXT_STATE_PROC: process(cur_state, cur_val1,cur_val2,cur_val3,cur_val4, PB2, PB3, PB4)
begin
case cur_state is
when s0 =>
if(PB4='1') then
next_state <= s0;
elsif(PB2='1') then
next_state <= s1;
end if;
case cur_val1 is
when 0 =>
if(PB3='1') then
next_val1 <= 1;
end if;
when 1 =>
if(PB3='1') then
next_val1 <= 2;
end if;
when 2 to 8 =>
if(PB3='1') then
next_val1 <= cur_val1 + 1;
end if;
when 9 =>
if(PB3='1') then
next_val1 <= 0;
end if;
end case;
when s1 =>
if(PB4='1') then
next_state <= s0;
elsif(PB2='1') then
next_state <= s1;
end if;
case cur_val2 is
when 0 =>
if(PB3='1') then
next_val2 <= 1;
end if;
when 1 =>
if(PB3='1') then
next_val2 <= 2;
end if;
when 2 to 8 =>
if(PB3='1') then
next_val2 <= cur_val1 + 1;
end if;
when 9 =>
if(PB3='1') then
next_val2 <= 0;
end if;
end case;
when s2 =>
if(PB4='1') then
next_state <= s0;
elsif(PB2='1') then
next_state <= s1;
end if;
case cur_val3 is
when 0 =>
if(PB3='1') then
next_val3 <= 1;
end if;
when 1 =>
if(PB3='1') then
next_val3 <= 2;
end if;
when 2 to 8 =>
if(PB3='1') then
next_val3 <= cur_val1 + 1;
end if;
when 9 =>
if(PB3='1') then
next_val3 <= 0;
end if;
end case;
when s3 =>
if(PB4='1') then
next_state <= s0;
elsif(PB2='1') then
next_state <= s1;
end if;
case cur_val4 is
when 0 =>
if(PB3='1') then
next_val4 <= 1;
end if;
when 1 =>
if(PB3='1') then
next_val4 <= 2;
end if;
when 2 to 8 =>
if(PB3='1') then
next_val4 <= cur_val1 + 1;
end if;
when 9 =>
if(PB3='1') then
next_val4 <= 0;
end if;
end case;
end case;
end process;
OUTPUT_VALUE_PROC:process(cur_val1, cur_val2, cur_val3, cur_val4)
begin
case cur_val1 is
when 0 => LED1 <= "0000";
when 1 => LED1 <= "0001";
when 2 => LED1 <= "0010";
when 3 => LED1 <= "0011";
when 4 => LED1 <= "0100";
when 5 => LED1 <= "0101";
when 6 => LED1 <= "0110";
when 7 => LED1 <= "0111";
when 8 => LED1 <= "1000";
when 9 => LED1 <= "1001";
end case;
case cur_val2 is
when 0 => LED1 <= "0000";
when 1 => LED1 <= "0001";
when 2 => LED1 <= "0010";
when 3 => LED1 <= "0011";
when 4 => LED1 <= "0100";
when 5 => LED1 <= "0101";
when 6 => LED1 <= "0110";
when 7 => LED1 <= "0111";
when 8 => LED1 <= "1000";
when 9 => LED1 <= "1001";
end case;
case cur_val3 is
when 0 => LED1 <= "0000";
when 1 => LED1 <= "0001";
when 2 => LED1 <= "0010";
when 3 => LED1 <= "0011";
when 4 => LED1 <= "0100";
when 5 => LED1 <= "0101";
when 6 => LED1 <= "0110";
when 7 => LED1 <= "0111";
when 8 => LED1 <= "1000";
when 9 => LED1 <= "1001";
end case;
case cur_val4 is
when 0 => LED1 <= "0000";
when 1 => LED1 <= "0001";
when 2 => LED1 <= "0010";
when 3 => LED1 <= "0011";
when 4 => LED1 <= "0100";
when 5 => LED1 <= "0101";
when 6 => LED1 <= "0110";
when 7 => LED1 <= "0111";
when 8 => LED1 <= "1000";
when 9 => LED1 <= "1001";
end case;
end process;
--SAVEANDRESET_PROC: process (save_type1, save_type2, save_type3, save_type4,PB4, PB1)
--begin
-- if (PB1= '1') then
-- save_type1 <= cur_val1;
-- save_type2 <= cur_val2;
-- save_type3 <= cur_val3;
-- save_type4 <= cur_val4;
-- elsif (PB4='1') then
-- save_type1 <= 0;
-- save_type2 <= 0;
-- save_type3 <= 0;
-- save_type4 <= 0;
-- if (PB1= '1') then
-- save_type1 <= cur_val1;
-- save_type2 <= cur_val2;
-- save_type3 <= cur_val3;
-- save_type4 <= cur_val4;
-- end if;
-- end if;
--end process;
--UNLOCK_PROC: process (save_type1, cur_val1, save_type2, cur_val2, save_type3, cur_val3, save_type4, cur_val4)
--begin
-- if(cur_val1 = save_type1 and
-- cur_val2 = save_type2 and
-- cur_val3 = save_type3 and
-- cur_val4 = save_type4 ) then
-- LED2<="1111";
-- LED1<="0000";
-- else
-- LED2<="0000";
-- LED1<="1111";
-- end if;
-- case unlock_type1 is
-- when 0 to 1 => unlock1 <= "1111";
-- when 2 to 9 => unlock1 <= "1111";
-- end case;
-- case unlock_type2 is
-- when 0 to 1 => unlock2 <= "1111";
-- when 2 to 9 => unlock2 <= "1111";
-- end case;
-- case unlock_type3 is
-- when 0 to 1 => unlock3 <= "1111";
-- when 2 to 9 => unlock3 <= "1111";
-- end case;
-- case unlock_type4 is
-- when 0 to 1 => unlock4 <= "1111";
-- when 2 to 9 => unlock4 <= "1111";
-- end case;
--
--end process;
OUTPUT_PROC:process(cur_state)
begin
case cur_state is
when s0 => LED2 <= "0001";
when s1 => LED2 <= "0011";
when s2 => LED2 <= "0111";
when s3 => LED2 <= "1111";
end case;
end process;
end behavioral;
我在这方面花了 4 周时间，这是我项目的一些基础知识，因为我必须逐个重新启动，以便排除为什么我的 LED1 和 LED2 也没有与按钮 (PB) 同步我仍在尝试弄清楚如何使其尽可能简单，因为我认为该代码仍然太长并且效率不高。这个警告和我知道的一些问题是在我在 iSim 中模拟后发生的，然后发现我的代码中有错误，但我无法弄清楚，现在我一无所知。 :(
感谢您的宝贵时间。
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哦，好的，非常感谢@user1155120提供的信息和进步。
标签： vhdl fpga xilinx xilinx-ise