【发布时间】：2017-05-26 07:06:54
【问题描述】：
我已经尝试了好几天，但它变得很沮丧，我无法抓住我的错误。如果有人能帮助我，我将不胜感激。以下是我的代码，其中我在顶部模块中有两个模块，在完美连接所有内容后，模块连接不知何故将无法工作。缺少从一个子模块到另一个子模块输入的输出（如果我从第一个子模块中删除我的始终代码）。如果始终代码在我的 vc_buffers 模块中未注释，我什至看不到 RTL 示意图中的 vc_buffers 模块。
完整代码如下：
`timescale 1ns / 1ps
`include "parameters.v"
module router(
clk,
rst,
flit_in,
flit_out
);
localparam flit_size = flit_ctrl + flit_data;
localparam fifo_depth = buffer_depth - 1;
localparam fifo_counter = fifo_depth;
input clk, rst;
input [flit_size-1:0] flit_in;
wire [flit_size-1:0] flit_in;
output [flit_size-1:0] flit_out;
wire [flit_size-1:0] flit_out;
wire [flit_size-1:0] flit_buffers_fifo;
wire vc_empty_sig, vc_wr_en_sig;
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////// VC BUFFER INST /////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
vc_buffers vc_buffers_0(
.clk(clk),
.rst(rst),
.vc_flit_in_0(flit_in),
.vc_flit_out_0(flit_buffers_fifo),
.vc_empty_0(vc_empty_sig),
.vc_wr_en_0(vc_wr_en_sig)
);
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////// FIFO INST //////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
fifo fifo_0(
.clk(clk),
.rst(rst),
.wr_en(vc_wr_en_sig),
.rd_en(),
.flit_in(flit_buffers_fifo),
.flit_out(flit_out),
.empty(vc_empty_sig),
.full()
);
endmodule
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////// VC BUFFER /////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
module vc_buffers(
clk,
rst,
vc_empty_0,
vc_flit_in_0,
vc_flit_out_0,
vc_wr_en_0
);
localparam flit_size = flit_ctrl + flit_data;
localparam fifo_depth = buffer_depth - 1;
localparam fifo_counter = fifo_depth;
input clk;
input rst;
input vc_empty_0;
wire vc_empty_0;
input [flit_size-1:0] vc_flit_in_0;
wire [flit_size-1:0] vc_flit_in_0;
output vc_wr_en_0;
reg vc_wr_en_0;
output [flit_size-1:0] vc_flit_out_0;
reg [flit_size-1:0] vc_flit_out_0;
always @(posedge clk)
begin
if(rst) begin
vc_wr_en_0 <= 0;
end else begin
if (vc_empty_0) begin
vc_wr_en_0 <= 1;
//vc_flit_out_tmp_0 <= vc_flit_in_0; //Assign flit on input pins of router port 0
//vc_flit_out_wire_0 <= vc_flit_in_0; //Assign flit on input pins of router port 0
vc_flit_out_0 <= vc_flit_in_0; //Assign flit on input pins of router port 0
vc_wr_en_0 <= 0;
end else begin
vc_wr_en_0 <= 0;
// Discard buffer as there is no space in vc input buffer
end
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////// FIFO //////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
module fifo(
clk,
rst,
wr_en,
rd_en,
flit_in,
flit_out,
empty,
full
);
localparam flit_size = flit_ctrl + flit_data;
localparam fifo_depth = buffer_depth - 1;
localparam fifo_counter = fifo_depth;
input clk;
input rst;
input wr_en;
input rd_en;
input [flit_size-1:0] flit_in;
output [flit_size-1:0] flit_out;
output full, empty;
wire rd_en;
wire wr_en;
wire [flit_size-1:0] flit_in;
reg [flit_size-1:0] flit_out;
reg [fifo_depth-1:0] head;
reg [fifo_depth-1:0] tail;
reg empty;
reg full;
reg [flit_size-1:0] memory [0:7];
always @(posedge clk)
begin
if ( rst) begin
empty <= 1;
full <= 0;
flit_out <= 0;
head <= 0;
tail <= 0;
end else begin
case ( {wr_en, rd_en} )
2'b10,
2'b1x,
2'b1z:
begin
if (empty) begin
memory[head] <= flit_in;
head <= (head == fifo_counter)?0:head+1;
end else begin
// do nothing
end
end
2'b01,
2'bx1,
2'bz1:
begin
flit_out <= memory[tail];
tail <= (tail == fifo_counter)?0:tail+1;
end
default:;
endcase
end
if (head == fifo_counter) begin
full <= 1;
empty <= 0;
end else begin
end
if (tail == fifo_counter) begin
empty <= 1;
full <= 0;
end else begin
end
end
endmodule
【问题讨论】：
标签： verilog