分频器和随后的信号边缘检测

Question

我对 VHDL 编程领域非常陌生，在实现分频器以及检测信号边缘时遇到了问题。该代码由 6 个按钮输入组成，每个按钮将在 50MHz 到 1KHz 的频率下运行并输出脉冲。

我正在尝试的问题如图所示：我在每个输入变量中都得到了 U。我在网上搜索了多个分频器，但到目前为止还没有成功。我也知道将代码上传到 fpga 的特定方式的实现以及在 xilinx 中进行模拟的另一种方式。

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;

entity armmov is
port(
    CLK_50MHz: in std_logic;
    rst  : in std_logic;
    BTN1 : in std_logic;
    BTN2 : in std_logic;
    BTN3 : in std_logic;
    BTN4 : in std_logic;
    BTN5 : in std_logic;
    BTN6 : in std_logic;
    PUL1 : out std_logic;
    PUL2 : out std_logic;
    PUL3 : out std_logic;
    PUL4 : out std_logic;
    PUL5 : out std_logic;
    PUL6 : out std_logic
);
end armmov;

architecture Behavioral of armmov is
signal Counter : integer := 1;
signal CLK_1KHz: std_logic := '0';

begin

process (CLK_50MHz,rst)
begin
        if (rst = '1') then
        Counter <= 1;
        CLK_1KHz <= '0';

    elsif(CLK_50MHz'event and CLK_50MHz='1') then
    Counter <= Counter + 1;
    if (Counter = 25000) then
    CLK_1KHz <= NOT CLK_1KHz;
    Counter <= 1;
    end if;
end if;
end process;


process(CLK_1KHz)
begin

if BTN1='1' then
PUL1<=CLK_1KHz;
else
PUL1 <='0';
end if;

if BTN2='1' then
PUL2<=CLK_1KHz;
else
PUL2 <='0';
end if;

if BTN3='1' then
PUL3<=CLK_1KHz;
else
PUL3 <='0';
end if;

if BTN4='1' then
PUL4<=CLK_1KHz;
else
PUL4 <='0';
end if;

if BTN1='1' then
PUL1<=CLK_1KHz;
else
PUL1<='0';
end if;

if BTN2='1' then
PUL2<=CLK_1KHz;
else
PUL2<='0';
end if;

if BTN3='1' then
PUL3<=CLK_1KHz;
else
PUL3<='0';
end if;

if BTN4='1' then
PUL4<=CLK_1KHz;
else
PUL4<='0';
end if;

if BTN5='1' then
PUL5<=CLK_1KHz;
else
PUL5<='0';
end if;

if BTN6='1' then
PUL6<=CLK_1KHz;
else
PUL6<='0';
end if;

end process;

end Behavioral;

Answer 1

输入值为“U”，因为这些信号未被驱动。您可以通过两种方法驱动这些信号。

1. 从仿真 GUI 强制时钟和常数。 Vivado GUI
2. 编写测试平台来驱动这些值

PS：不要使用 ieee.std_logic_unsigned 和类似的库，因为它们没有标准化。相反，使用 ieee.numeric_std.all

几个有用的学习VHDL的网站：

1. https://vhdlwhiz.com/basic-vhdl-tutorials/

2. https://insights.sigasi.com/tech/

3. https://www.nandland.com/articles/coding-style-recommendations-vhdl-verilog.html

Answer 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity armmov is
    port
    (
        clk_50mhz: in std_logic;
        reset: in std_logic;
        btn1: in std_logic;
        btn2: in std_logic;
        btn3: in std_logic;
        btn4: in std_logic;
        btn5: in std_logic;
        btn6: in std_logic;
        pul1: out std_logic;
        pul2: out std_logic;
        pul3: out std_logic;
        pul4: out std_logic;
        pul5: out std_logic;
        pul6: out std_logic
    );
end armmov;

architecture behavioral of armmov is
    signal counter: natural := 0;
    signal clk_1khz: std_logic := '0';

begin

    process(clk_50mhz, reset)
    begin
        if reset then
            counter <= 0;
            clk_1khz <= '0';
        elsif rising_edge(clk_50mhz) then
            counter <= counter + 1;
            if counter = 25000 then
                clk_1khz <= not clk_1khz;
                counter <= 0;
            end if;
        end if;
    end process;

    pul1 <= clk_1khz and btn1;
    pul2 <= clk_1khz and btn2;
    pul3 <= clk_1khz and btn3;
    pul4 <= clk_1khz and btn4;
    pul5 <= clk_1khz and btn5;
    pul6 <= clk_1khz and btn6;

end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity armmov_tb is
end;

architecture V1 of armmov_tb is

    constant SYS_CLOCK_FREQ: real := 50000000.0;  -- Hz
    constant SYS_CLOCK_PERIOD: time := 1.0 sec / SYS_CLOCK_FREQ;

    signal halt_clk_50mhz: boolean := false;
    signal clk_50mhz: std_logic := '0';

    signal reset: std_logic;
    signal btn1: std_logic;
    signal btn2: std_logic;
    signal btn3: std_logic;
    signal btn4: std_logic;
    signal btn5: std_logic;
    signal btn6: std_logic;
    signal pul1: std_logic;
    signal pul2: std_logic;
    signal pul3: std_logic;
    signal pul4: std_logic;
    signal pul5: std_logic;
    signal pul6: std_logic;

    component armmov is
        port
        (
            clk_50mhz: in std_logic;
            reset: in std_logic;
            btn1: in std_logic;
            btn2: in std_logic;
            btn3: in std_logic;
            btn4: in std_logic;
            btn5: in std_logic;
            btn6: in std_logic;
            pul1: out std_logic;
            pul2: out std_logic;
            pul3: out std_logic;
            pul4: out std_logic;
            pul5: out std_logic;
            pul6: out std_logic
        );
    end component;

begin

    SysClockGenerator: process
    begin
        while not halt_clk_50mhz loop
            clk_50mhz <= '1';
            wait for SYS_CLOCK_PERIOD / 2.0;
            clk_50mhz <= '0';
            wait for SYS_CLOCK_PERIOD / 2.0;
        end loop;
        wait;
    end process SysClockGenerator;

    StimulusProcess: process
    begin
        btn1 <= '0';
        btn2 <= '0';
        btn3 <= '0';
        btn4 <= '0';
        btn5 <= '0';
        btn6 <= '0';

        reset <= '1';
        wait for SYS_CLOCK_PERIOD;
        reset <= '0';
        wait for SYS_CLOCK_PERIOD;

        btn1 <= '1'; wait for 50 * 25000 * SYS_CLOCK_PERIOD; btn1 <= '0'; wait for 50 * 25000 * SYS_CLOCK_PERIOD;
        btn2 <= '1'; wait for 50 * 25000 * SYS_CLOCK_PERIOD; btn2 <= '0'; wait for 50 * 25000 * SYS_CLOCK_PERIOD;
        btn3 <= '1'; wait for 50 * 25000 * SYS_CLOCK_PERIOD; btn3 <= '0'; wait for 50 * 25000 * SYS_CLOCK_PERIOD;
        btn4 <= '1'; wait for 50 * 25000 * SYS_CLOCK_PERIOD; btn4 <= '0'; wait for 50 * 25000 * SYS_CLOCK_PERIOD;
        btn5 <= '1'; wait for 50 * 25000 * SYS_CLOCK_PERIOD; btn5 <= '0'; wait for 50 * 25000 * SYS_CLOCK_PERIOD;
        btn6 <= '1'; wait for 50 * 25000 * SYS_CLOCK_PERIOD; btn6 <= '0'; wait for 50 * 25000 * SYS_CLOCK_PERIOD;

        wait for 50 * SYS_CLOCK_PERIOD;
        halt_clk_50mhz <= true;

        wait;
    end process;

    DUT: armmov
        port map
        (
            clk_50mhz => clk_50mhz,
            reset => reset,
            btn1 => btn1,
            btn2 => btn2,
            btn3 => btn3,
            btn4 => btn4,
            btn5 => btn5,
            btn6 => btn6,
            pul1 => pul1,
            pul2 => pul2,
            pul3 => pul3,
            pul4 => pul4,
            pul5 => pul5,
            pul6 => pul6
        );

end architecture;