高阻信号不进入测试台【VHDL】

Question

首先，我是 VHDL 的新手，我正在尝试创建一个 RAM 模型（或类似的东西）。该模型工作正常，我开始构建我的测试台，但它没有重现从原始模型生成的信号文件的行为。主要问题是高阻信号“** Z ”变成了“ U ”（未定义），复位信号后，值（ X“0000” *) 变成了“ * X”。**“（未知）。我在测试台中有 3 个主要测试，用标签 Test_N 标记，但第一个，最后一个由于上述错误而失败。因此，带有 Test_1 和 Test_3 的行被注释掉了。下面是 RAM.vhd 和 RAM_TB.vhd 的代码，附有两张测试它们的屏幕截图。

RAM.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RAM is
    port (CLK : in std_logic; -- Clock
          R   : in std_logic; -- Reset
          WR  : in std_logic; -- Write
          AE  : in std_logic; -- Address saving in temp.    
          OE  : in std_logic; -- Signal about output word
          AD  : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data) 
end RAM;

architecture BEH of RAM is
type MEM2KX16 is array(0 to 2047) of std_logic_vector(AD'range);
constant RAM_init : MEM2KX16 := (X"0000", others=>X"0000"); -- initial memory state
signal do : std_logic_vector(AD'range); -- signal for data output
signal addr : std_logic_vector(10 downto 0); -- 2047 = 0111 1111 1111, 11 bits needed
signal addri : natural;
signal RAM_out : MEM2KX16; -- For debug purposes
begin
    RG_ADDR : process (CLK, R)
    begin
        if (R = '1') then
            addr <= "00000000000"; -- Reset address
        elsif rising_edge(CLK) and AE = '1' then
            addr <= AD(10 downto 0); -- Receive address
        end if;
    end process;
    
    RAM2K : process (CLK, addr, addri)
    variable RAM : MEM2KX16 := RAM_init;
    begin
        addri <= to_integer(unsigned(addr(10 downto 0)));
        if rising_edge(CLK) then
            if (WR = '1') then -- Write to memory
                RAM(addri) := AD(15 downto 0);
            end if;
            if (R = '1') then -- Reset memory 
                do <= X"0000";
            else
                do <= RAM(addri); -- Return data from memory
            end if;
        end if;
    RAM_out <= RAM; -- For debug purposes
    end process;
    
    TRI : AD <= do when (OE = '1') -- Three-state buffer
    else "ZZZZZZZZZZZZZZZZ";
end architecture;

RAM_TB.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RAM_TB is
end entity;

architecture RAM_TB_arch of RAM_TB is
    component RAM 
    port (CLK : in std_logic; -- Clock
          R   : in std_logic; -- Reset
          WR  : in std_logic; -- Write
          AE  : in std_logic; -- Address saving in temp.    
          OE  : in std_logic; -- Signal about output word
          AD  : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data) 
    end component;
    constant T : time := 20 ns;
    
    signal CLK_TB, R_TB, WR_TB, AE_TB, OE_TB : std_logic;
    signal AD_TB : std_logic_vector(15 downto 0);
    
    begin
        
        DUT : RAM port map (CLK_TB, R_TB, WR_TB, AE_TB, OE_TB, AD_TB);
        
        process
        begin
            CLK_TB <= '0';
            wait for T/2;
            CLK_TB <= '1';
            wait for T/2;
        end process;
        
        STIMULUS : process
        variable value : std_logic_vector(AD_TB'range) := X"FFFF";
        variable addr  : std_logic_vector(AD_TB'range) := X"0004"; 
        begin
            -- Test ZZZZ output of AD
            R_TB  <= '0'; -- No reset
            WR_TB <= '0'; -- No write
            AE_TB <= '0'; -- No address 
            OE_TB <= '0'; -- No output
            wait for 2*T;
            --Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
            
            -- Test input of AD
            R_TB  <= '0'; -- No reset
            WR_TB <= '0'; -- No write
            AE_TB <= '1'; -- Read address 
            OE_TB <= '0'; -- No output
            AD_TB <= addr; -- Address RAM(4)
            wait for T;
            WR_TB <= '1'; -- Write
            AE_TB <= '0'; -- Do not read address
            AD_TB <= value; -- Data to write
            wait for T;
            -- Test output of AD
            WR_TB <= '0'; -- No write
            OE_TB <= '1'; -- Output data from RAM
            wait for T;
            Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
            
            -- Test Reset
            R_TB <= '1'; -- Reset
            wait for T;
            --Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
            
            wait;      
        end process;
end architecture;

RAM 波形

RAM 测试台波形

测试台有什么问题？非常感谢您的帮助！

更新 1

我在评论中遵循了布赖恩的建议，部分解决了问题。现在，第一次测试中的未初始化状态变成了预期的高阻抗状态。但是代替零的状态“X”仍然存在。

更新了 RAM_TB.vhd 中的代码

signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');

RAM_TB 波形（更新 1）

更新 2

感谢@Tricky 在评论部分提供的解决方案。

为 Test_3 更新了 RAM_TB.vhd 中的代码

    R_TB <= '1'; -- Reset
    AD_TB <= "ZZZZZZZZZZZZZZZZ";
    wait for T;

RAM_TB 波形（更新 2）

Answer 1

在@BrianDrummond 和@Tricky 的cmets 的指导下，我可以发布我的问题的答案。问题的原因和解决方法可以在问题下的cmet中找到。

RAM_TB.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RAM_TB is
end entity;

architecture RAM_TB_arch of RAM_TB is
    component RAM 
    port (CLK : in std_logic; -- Clock
          R   : in std_logic; -- Reset
          WR  : in std_logic; -- Write
          AE  : in std_logic; -- Address saving in temp.    
          OE  : in std_logic; -- Signal about output word
          AD  : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data) 
    end component;
    constant T : time := 20 ns;
    
    signal CLK_TB, R_TB, WR_TB, AE_TB, OE_TB : std_logic;
    signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');
    
    begin
        
        DUT : RAM port map (CLK_TB, R_TB, WR_TB, AE_TB, OE_TB, AD_TB);
        
        process
        begin
            CLK_TB <= '0';
            wait for T/2;
            CLK_TB <= '1';
            wait for T/2;
        end process;
        
        STIMULUS : process
        variable value : std_logic_vector(AD_TB'range) := X"FFFF";
        variable addr  : std_logic_vector(AD_TB'range) := X"0004"; 
        begin
            -- Test ZZZZ output of AD
            R_TB  <= '0'; -- No reset
            WR_TB <= '0'; -- No write
            AE_TB <= '0'; -- No address 
            OE_TB <= '0'; -- No output
            wait for 2*T;
            Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
            
            -- Test input of AD
            R_TB  <= '0'; -- No reset
            WR_TB <= '0'; -- No write
            AE_TB <= '1'; -- Read address 
            OE_TB <= '0'; -- No output
            AD_TB <= addr; -- Address RAM(4)
            wait for T;
            WR_TB <= '1'; -- Write
            AE_TB <= '0'; -- Do not read address
            AD_TB <= value; -- Data to write
            wait for T;
            -- Test output of AD
            AD_TB <= "ZZZZZZZZZZZZZZZZ";
            WR_TB <= '0'; -- No write
            OE_TB <= '1'; -- Output data from RAM
            wait for T;
            Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
            
            -- Test Reset
            wait for T;
            R_TB <= '1'; -- Reset
            AD_TB <= "ZZZZZZZZZZZZZZZZ";
            wait for T;
            Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
            
            wait;      
        end process;
end architecture;