【发布时间】:2018-12-25 18:39:29
【问题描述】:
我有 VHDL 代码应该执行以下操作:当 KEY(0)(RESET) 被按下时,下一个上升时钟启动该过程(50MHz)。它设置 status_flag 并且一个新进程查看 status_flag 并且每 1000000(+ const)clk 周期更新一个称为 DAC 的值。我想随着 clk-cntr 的更新,它需要几个时钟周期,因此是常数。 (我使用了数据记录器,我可以看到~20.02ms)在第二个过程的底部,clk-cntr 被重置为零。目标是在 KEY(0) 被按下后经历第二个过程,并等待下一次 KEY 按下。可以看到,我将 status_flag 注释掉了,因为编译器的响应是“无法解析多个常量驱动程序”。如何重置 status_flag 或类似内容以让代码等待 KEY(0)?我正在使用实时响应而不是模拟。
-- ---------------------------------------------------------------------
-- Global signals ------------------------------------------------------
-- ---------------------------------------------------------------------
CLK : in std_logic;
RESET : in std_logic;
);
结束实体test_top;
test_top 的架构 rtl 是
shared variable status_flag : std_logic;
signal clk_cntr : unsigned(31 downto 0);
signal DAC : std_logic_vector(11 downto 0);
开始
DAC_Out_Rising_Edge: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then -- KEY(0) switch
status_flag := '1'; -- The encoder is triggered on the rising edge of the clock
end if;
end if;
end process;
Servo_routine: process(CLK)
begin
if rising_edge(CLK) then --
if (status_flag = '1') then
clk_cntr <= clk_cntr + 1;
if clk_cntr = 4 then
DAC <= "000000000000"; -- initialize value
end if;
if clk_cntr = 1000000 then
DAC <= "000000000010";
end if;
if clk_cntr = 2000000 then
DAC <= "000000000100";
end if;
if clk_cntr = 3000000 then
DAC <= "000000001000";
end if;
if clk_cntr = 4000000 then
DAC <= "000000010000";
end if;
if clk_cntr = 5000000 then
DAC <= "000000100000";
end if;
if clk_cntr = 6000000 then
DAC <= "000001000000";
end if;
if clk_cntr = 7000000 then
DAC <= "000010000000";
end if;
if clk_cntr = 8000000 then
DAC <= "000100000000";
end if;
if clk_cntr = 9000000 then
DAC <= "001000000000";
end if;
if clk_cntr = 1000000 then
DAC <= "000100000000";
end if;
if clk_cntr = 1100000 then
DAC <= "000010000000";
end if;
if clk_cntr = 1200000 then
DAC <= "000001000000";
end if;
if clk_cntr = 1300000 then
DAC <= "000000100000";
end if;
if clk_cntr = 14000000 then
DAC <= "000000010000";
end if;
if clk_cntr = 15000000 then
DAC <= "000000001000";
end if;
if clk_cntr = 16000000 then
DAC <= "000000000100";
end if;
if clk_cntr = 17000000 then
DAC <= "000000000010";
end if;
if clk_cntr = 18000000 then
DAC <= "000000000000";
end if;
if clk_cntr > 18000000 then
DAC <= "000000000000"; -- resets flags/data
clk_cntr <= (others => '0'); -- resets flags/data
if RESET = '0' then
--status_flag := '0'; -- The encoder is reset
end if;
end if;
end if;
end if;
end process;
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