3-8译码器/4-16译码器的verilo实现（组合逻辑）

module code3_8(a,b,c,out);
    
    //输入端口
    input a;
    input b;
    input c;
    
    //输出端口
    output reg [7:0]out;        //【】定义out信号为8位的位宽，高位在前，低位在后
    
    //所有在always@中要赋值的信号都必须定义为reg型
    always@(a,b,c)begin            //abc为敏感信号
        case({a,b,c})        // {}拼接三个信号为一个新的信号
            3\'b000:out = 8\'b0000_0001;        //下划线为占位符，无实际意义
            3\'b001:out = 8\'b0000_0010;
            3\'b010:out = 8\'b0000_0100;
            3\'b011:out = 8\'b0000_1000;
            3\'b100:out = 8\'b0001_0000;
            3\'b101:out = 8\'b0010_0000;
            3\'b110:out = 8\'b0100_0000;
            3\'b111:out = 8\'b1000_0000;
            //default:out = xxxxxxxx;    如果不必枚举全部情况，则用default表示剩余情况
        endcase
    end  

endmodule

`timescale 1ns/1ns

module code3_8_tb;

    reg a;
    reg b;
    reg c;
    
    wire [7:0] out;
    code3_8 u1(
        .a(a),
        .b(b),
        .c(c),
        .out(out)
    );

    initial begin
        a = 0;b = 0;c = 1;
        #200;
        a = 0;b = 1;c = 0;
        #200;
        a = 0;b = 1;c = 1;
        #200;
        a = 1;b = 0;c = 0;
        #200;
        a = 1;b = 0;c = 1;
        #200;
        a = 1;b = 1;c = 0;
        #200;
        a = 1;b = 1;c = 1;
        #200;
        a = 0;b = 0;c = 0;
        #200;
        
        $stop;    
        
        end
    
endmodule

 4-16译码器增加一个输入端口即可