Verilog流水线乘法器

主要内容：

　　1. 4位流水线乘法器

　　2. 8位流水线乘法器

　　3. 16位流水线乘法器

　　

 1 module multi_4bits_pipelining(mul_a, mul_b, clk, rst_n, mul_out);
 2     
 3     input [3:0] mul_a, mul_b;
 4     input       clk;
 5     input       rst_n;
 6     output [7:0] mul_out;
 7 
 8     reg [7:0] mul_out;
 9 
10     reg [7:0] stored0;//stored0,...stored3用来存逐位相乘的中间结果  
11     reg [7:0] stored1;
12     reg [7:0] stored2;
13     reg [7:0] stored3;
14 
15     reg [7:0] add01;//中间结果变量  
16     reg [7:0] add23;
17 
18     always @(posedge clk or negedge rst_n) begin
19         if(!rst_n) begin
20             mul_out <= 0;
21             stored0 <= 0;
22             stored1 <= 0;
23             stored2 <= 0;
24             stored3 <= 0;
25             add01 <= 0;
26             add23 <= 0;
27         end
28         else begin
29             stored0 <= mul_b[0]? {4'b0, mul_a} : 8'b0;//如果被乘数倒数第一位不为零，则与乘数相乘结果为{4'b0,mul_a}  
30             stored1 <= mul_b[1]? {3'b0, mul_a, 1'b0} : 8'b0;
31             stored2 <= mul_b[2]? {2'b0, mul_a, 2'b0} : 8'b0;
32             stored3 <= mul_b[3]? {1'b0, mul_a, 3'b0} : 8'b0;
33 
34             add01 <= stored1 + stored0;
35             add23 <= stored3 + stored2;
36 
37             mul_out <= add01 + add23;//最终结果  
38         end
39     end
40 
41 endmodule

　1.1 4位流水线乘法器案例

2. 8位流水线乘法器

 1 module multiplier_8(clk,rst_n,mul_a,mul_b,result
 2     );
 3 input clk;
 4 input rst_n;
 5 input[7:0] mul_a;
 6 input[7:0] mul_b;
 7 output[15:0] result;
 8 reg[15:0] result;
 9 reg[15:0] store7;
10 reg[15:0] store6;
11 reg[15:0] store5;
12 reg[15:0] store4;
13 reg[15:0] store3;
14 reg[15:0] store2;
15 reg[15:0] store1;
16 reg[15:0] store0;
17 reg[15:0] add01;
18 reg[15:0] add23;
19 reg[15:0] add45;
20 reg[15:0] add67;
21 reg[15:0] add0123;
22 reg[15:0] add4567;
23 always @ (posedge clk or negedge rst_n)
24 
25 begin
26  if(!rst_n)
27  begin
28   store7 <= 16'b0;
29   store6 <= 16'b0;
30   store5 <= 16'b0;
31   store4 <= 16'b0;
32   store6 <= 16'b0;
33   store2 <= 16'b0;
34   store1 <= 16'b0;
35   store0 <= 16'b0;
36   add01  <= 16'b0;
37   add23  <= 16'b0;
38   add45  <= 16'b0;
39   add67  <= 16'b0;
40   add0123  <= 16'b0;
41   add4567  <= 16'b0;
42  end
43  else
44 
45  begin
46   store0 <= mul_b[0] ? {8'b0,mul_a}:16'b0;
47   store1 <= mul_b[1] ? {7'b0,mul_a,1'b0}:16'b0;
48   store2 <= mul_b[2] ? {6'b0,mul_a,2'b0}:16'b0;
49   store3 <= mul_b[3] ? {5'b0,mul_a,3'b0}:16'b0;
50   store4 <= mul_b[4] ? {4'b0,mul_a,4'b0}:16'b0;
51   store5 <= mul_b[5] ? {3'b0,mul_a,5'b0}:16'b0;
52   store6 <= mul_b[6] ? {2'b0,mul_a,6'b0}:16'b0;
53   store7 <= mul_b[7] ? {1'b0,mul_a,7'b0}:16'b0;
54 
55   add67  <= store7+store6;
56   add45  <= store5+store4;
57   add23  <= store3+store2;
58   add01  <= store1+store0;
59   add0123  <= add01 + add23;
60   add4567  <= add45 + add67;
61   result <= add0123 + add4567;
62  end
63 end
64 endmodule

multiplier_8