用Verilog来实现d触发器2分频的Verilog hdl程序

module divide_2(clk,rst,clk_out);

input clk,rst;
output clk_out;

reg clk_out;

always @(posedge clk or negedge rst)
 if(!rst)
  begin
   clk_out<=0;
  end
 else
  begin
   clk_out<=~clk_out;
  end

endmodule