scan chain的原理和实现——8.AT SPEED Test & OCC

last_shift launch mode （低速测试）

system_clock launch mode ( launch on capture)

1.at speed test structure and OCC Controller

 

 

2.OCC Controller

当使用set_dft_configuration -clock_controller enable运行insert_dft

DFT编译器会将DFT_clk_mux和DFT_clk_chain组件添加到网表中。

２.１OCC Controller的结构

①fast pulse controller

 ②clock selection circuit

 

 DFT_clk_mux I/O ports

port name	direction	function
reset	input	1重置控制器，0允许控制器运行
test_mode	input	1控制时钟，0无条件选择快速时钟
pll_bypass	input	1选择slow_clk，0选择clock switch-over操作
scan_en	input	调解clock switch-over操作
clk_enable[m:0]	input	从时钟链捕获脉冲控制
fast_clk[n:0]	input	PLL的快速时钟
slow_clk	input	ATE时钟
clk[n:0]	output	扫描触发器output clock

 

２.２　OCC脚本示例：

Reference clock ==> ref_clk
ATE clock ==> ate_clk
PLL clock (output of pll) ==> pll/out
External clock ==> ext_clk

#test_default period is 100
set test_default_period 100、
# specify the reference clock with proper period and timing (only one command for reference clock)
set_dft_signal -yiew exist -type refclock -period 73 -timing { 40 50} -port ref_clk
# specify the pll clock (output from PLL), as type oscillator
set_dft_signal -view exist -type oscillator -hookup_pin pll/out #Specify the ATE clock,as type oscillator and scanclock both
set_dft_signal -view exist -type oscillator -port ate_clk
set_dft_signal -view exist-type scanclock -tining {50 80} -port ate_clk
#specify the external clock (if any)
set_dft_signal -view exist -type scanclock -timing {50 80} -port ext_clk

clock period is not equal to ATE clock period

#test_default period is 100
set test_default period 100
# specify the reference clock (as type refclock and Masterclock )
set_dft_signal -view exist -type MasterClock -timing {50 80} -port ref_clk
set_dft_signal -view exist -type refclock -period 100 -timing {50 80) -port ref_clk
#specify the pll clock (output from PLL),as type oscillator
set_dft_signal -view exist -type oscillator -hookup_pin pll/out
#Specify the ATE clock,as type oscillator and scanclock both
set_dft_signal -view exist -type oscillator -port ate_clk
set_dft_signal -view exist -type scanclock -timing {50 80} -port ate_clk
#specify the external clock(if any)
set_dft_signal -view exist -type scanclock -timing (50 80} -port ext_clk

clock period is equal to ATE clock period