同步FIFO的verilog描述

 1 /******************************************************
 2 A fifo controller verilog description.
 3 ******************************************************/
 4 module fifo(datain, rd, wr, rst, clk, dataout, full, empty);
 5 input [7:0] datain;
 6 input rd, wr, rst, clk;
 7 output [7:0] dataout;
 8 output full, empty;
 9 wire [7:0] dataout;
10 reg full_in, empty_in;
11 reg [7:0] mem [15:0];
12 reg [3:0] rp, wp;//其实是一个循环读写的过程,4位二进制数刚好16个状态，也即指示16个深度
13 assign full = full_in;
14 assign empty = empty_in;
15 // memory read out
16 assign dataout = mem[rp];
17 // memory write in
18 always@(posedge clk) begin
19     if(wr && ~full_in) mem[wp]<=datain;
20 end
21 // memory write pointer increment
22 always@(posedge clk or negedge rst) begin
23     if(!rst) wp<=0;
24     else begin
25       if(wr && ~full_in) wp<= wp+1'b1;
26     end
27 end
28 // memory read pointer increment
29 always@(posedge clk or negedge rst)begin
30     if(!rst) rp <= 0;
31     else begin
32       if(rd && ~empty_in) rp <= rp + 1'b1;
33     end
34 end
35 // Full signal generate
36 always@(posedge clk or negedge rst) begin
37     if(!rst) full_in <= 1'b0;
38     else begin
39       if( (~rd && wr)&&((wp==rp-1)||(rp==4'h0&&wp==4'hf)))
40           full_in <= 1'b1;
41       else if(full_in && rd) full_in <= 1'b0;
42     end
43 end
44 // Empty signal generate
45 always@(posedge clk or negedge rst) begin
46     if(!rst) empty_in <= 1'b1;
47     else begin
48       if((rd&&~wr)&&(rp==wp-1 || (rp==4'hf&&wp==4'h0)))
49         empty_in<=1'b1;
50       else if(empty_in && wr) empty_in<=1'b0;
51     end
52 end
53 endmodule 

同步FIFO