一、第一阶段，无修改
二、第二阶段
u-boot-1.3.4\lib_arm\board.c
1.增加头文件
2.增加版本号
3.start_armboot中初始化部分
板级初始化部分init_sequence->board_init
3.1创建新单板资源头文件include\asm-arm\arch-at91sam9\at91sam9m10g45ek.h(地址与中断号)
文件书写思路：
1.参考同系列芯片的at91sam9263.h文件
2.外设标识符
3.用户外围物理基地址
4.系统外设物理基地址（基于系统控制寄存器）
5.内部存储基地址
参照图表：
附上源代码:
1 #ifndef AT91SAM9G45_H 2 #define AT91SAM9G45_H 3 4 /* 5 * Peripheral identifiers/interrupts. 6 */ 7 #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 8 #define AT91_ID_SYS 1 /* System Controller Interrupt */ 9 #define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ 10 #define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ 11 #define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ 12 #define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ 13 #define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ 14 #define AT91SAM9G45_ID_US0 7 /* USART 0 */ 15 #define AT91SAM9G45_ID_US1 8 /* USART 1 */ 16 #define AT91SAM9G45_ID_US2 9 /* USART 2 */ 17 #define AT91SAM9G45_ID_US3 10 /* USART 3 */ 18 #define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ 19 #define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ 20 #define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ 21 #define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ 22 #define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ 23 #define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ 24 #define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ 25 #define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ 26 #define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ 27 #define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ 28 #define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ 29 #define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ 30 #define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ 31 #define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ 32 #define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ 33 #define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ 34 #define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ 35 #define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ 36 #define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ 37 #define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ 38 #define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ 39 40 /* 41 * User Peripheral physical base addresses. 42 */ 43 #define AT91SAM9G45_BASE_UDPHS 0xfff78000 44 #define AT91SAM9G45_BASE_TC0 0xfff7c000 45 #define AT91SAM9G45_BASE_TC1 0xfff7c040 46 #define AT91SAM9G45_BASE_TC2 0xfff7c080 47 #define AT91SAM9G45_BASE_MCI0 0xfff80000 48 #define AT91SAM9G45_BASE_TWI0 0xfff84000 49 #define AT91SAM9G45_BASE_TWI1 0xfff88000 50 #define AT91SAM9G45_BASE_US0 0xfff8c000 51 #define AT91SAM9G45_BASE_US1 0xfff90000 52 #define AT91SAM9G45_BASE_US2 0xfff94000 53 #define AT91SAM9G45_BASE_US3 0xfff98000 54 #define AT91SAM9G45_BASE_SSC0 0xfff9c000 55 #define AT91SAM9G45_BASE_SSC1 0xfffa0000 56 #define AT91SAM9G45_BASE_SPI0 0xfffa4000 57 #define AT91SAM9G45_BASE_SPI1 0xfffa8000 58 #define AT91SAM9G45_BASE_AC97C 0xfffac000 59 #define AT91SAM9G45_BASE_TSC 0xfffb0000 60 #define AT91SAM9G45_BASE_ISI 0xfffb4000 61 #define AT91SAM9G45_BASE_PWMC 0xfffb8000 62 #define AT91SAM9G45_BASE_EMAC 0xfffbc000 63 #define AT91SAM9G45_BASE_AES 0xfffc0000 64 #define AT91SAM9G45_BASE_TDES 0xfffc4000 65 #define AT91SAM9G45_BASE_SHA 0xfffc8000 66 #define AT91SAM9G45_BASE_TRNG 0xfffcc000 67 #define AT91SAM9G45_BASE_MCI1 0xfffd0000 68 #define AT91SAM9G45_BASE_TC3 0xfffd4000 69 #define AT91SAM9G45_BASE_TC4 0xfffd4040 70 #define AT91SAM9G45_BASE_TC5 0xfffd4080 71 #define AT91_BASE_SYS 0xffffe200 72 73 /* 74 * System Peripherals (offset from AT91_BASE_SYS) 75 */ 76 #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) 77 #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) 78 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 79 #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) 80 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 81 #define AT91_DMA (0xffffec00 - AT91_BASE_SYS) 82 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) 83 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 84 #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) 85 #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) 86 #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) 87 #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) 88 #define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) 89 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 90 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 91 #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 92 #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) 93 #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) 94 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 95 #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 96 #define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) 97 98 #define AT91_USART0 AT91SAM9G45_BASE_US0 99 #define AT91_USART1 AT91SAM9G45_BASE_US1 100 #define AT91_USART2 AT91SAM9G45_BASE_US2 101 #define AT91_USART3 AT91SAM9G45_BASE_US3 102 103 /* 104 * Internal Memory. 105 */ 106 #define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 107 #define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ 108 109 #define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ 110 #define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ 111 112 #define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ 113 #define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ 114 #define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */ 115 #define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ 116 #define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ 117 118 #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 119 120 121 #endif