AHB总线接口RAM

 1 //##################################################################################################
 2 //  Project     : AMBA AHB RAM
 3 //  Author      : Lyu Yang
 4 //  Date        : 2020-05-10
 5 //  Description : AHB RAM
 6 //##################################################################################################
 7 module ahb_ram (
 8     input   wire                hclk        ,
 9     input   wire                hreset_n    ,
10     input   wire                hsel        ,
11     input   wire    [1:0]       htrans      ,
12     input   wire                hwrite      ,
13     input   wire    [2:0]       hsize       ,
14     input   wire    [31:0]      haddr       ,
15     input   wire    [31:0]      hwdata      ,
16     input   wire                hready_in   ,
17     output  reg     [31:0]      hrdata      ,
18     output                      hready_out  ,
19     output  wire    [1:0]       hresp
20 );
21 
22 localparam      MEM_SIZE = 4096;
23 
24 integer         k;
25 wire            hbus_ena;
26 reg             hbus_ena_d;
27 reg     [3:0]   mem_wstrb;
28 reg     [31:0]  mem_addr;
29 reg     [31:0]  mem[MEM_SIZE-1:0];
30 
31 // Memory Init
32 initial $readmemh("app_test.txt", mem);
33 
34 // AHB response always OKAY
35 assign hresp = 2'h0;
36 assign hready_out = 1'b1;
37 assign hbus_ena = hsel & hready_in & htrans[1];
38 
39 always @(posedge hclk, negedge hreset_n)
40     if(~hreset_n)
41         hbus_ena_d <= 1'b0;
42     else
43         hbus_ena_d <= hbus_ena;
44 
45 always @(posedge hclk, negedge hreset_n)
46     if(~hreset_n)
47         mem_addr <= 32'd0;
48     else if(hbus_ena)
49         mem_addr <= haddr;
50 
51 always @(posedge hclk, negedge hreset_n)
52     if(~hreset_n)
53         mem_wstrb <= 4'h0;
54     else if(hbus_ena & hwrite) begin
55         case(hsize)
56             3'b000: begin
57                 case(haddr[1:0])
58                     2'b00: mem_wstrb <= 4'b0001;
59                     2'b01: mem_wstrb <= 4'b0010;
60                     2'b10: mem_wstrb <= 4'b0100;
61                     2'b11: mem_wstrb <= 4'b1000;
62                 endcase
63             end
64             3'b001: begin
65                 case(haddr[0])
66                     1'b0: mem_wstrb <= 4'b0011;
67                     1'b1: mem_wstrb <= 4'b1100;
68                 endcase
69             end
70             3'b010: begin
71                 mem_wstrb <= 4'b1111;
72             end
73             default: begin
74                 mem_wstrb <= 4'b0000;
75             end
76         endcase
77     end
78     else begin
79         mem_wstrb <= 4'b0000;
80     end
81 
82 always @(posedge hclk)
83     for(k=0; k<4; k=k+1)
84         if(mem_wstrb[k] && hbus_ena_d)
85             mem[mem_addr[31:2]][k*8+:8] <= hwdata[k*8+:8];
86 
87 always @(posedge hclk)
88     if(hbus_ena)
89         hrdata <= mem[haddr[31:2]];
90 
91 endmodule