The keep attribute is used for a wire or net node. For example:
In Verilog:
wire my_wire /* synthesis keep = 1 */:
In VHDL:
signal my_signal: bit;
attribute syn_keep : boolean;
attribute syn_keep of my_signal: signal is true;
The preserve attribute is used for a register. For example:
In Verilog:
reg my_reg /* synthesis preserve = 1 */:
In VHDL:
signal my_reg: stdlogic;
attribute preserve : boolean;
attribute preserve of my_signal: signal is true;