Error (10200): Verilog HDL Conditional Statement error at ps2_con_cmd.v(11): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
一个进程有两个驱动信号。
错误如下：
always@(posedge i_clk or negedge i_rst)
if(i_rst) //修改为if(！i_rst)
begin
r_ps2_data<=4'b0001;
end
else if(r_ps2_data)
case(i_ps2_data)
8'h1d:
r_ps2_data<={r_ps2_data[2:0],r_ps2_data[3]};
8'h22:
r_ps2_data<={r_ps2_data[0],r_ps2_data[3:1]};
8'h14:
r_ps2_data<={r_ps2_data[0],r_ps2_data[1],r_ps2_data[2],r_ps2_data[3]};
endcase
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