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逻辑冲突
1 //定义模块输入输出 2 module LED_LIGHT 3 ( 4 input clk_in, 5 input rst_n_in, 6 output [7:0]led 7 ); 8 //****************************************************** 9 parameter CLK_DIV_PERIOD = 25_000_000;//频率25Mhz 10 11 reg [7:0]state; 12 reg [3:0]cnt; 13 //******************************************************** 14 clk_1s U1 //1s模块 15 ( 16 .clk_in(clk_in), 17 .rst_n_in(rst_n_in), 18 .clk_1s(clk_1s) 19 ); 20 //************************************************************ 21 always@(posedge clk_1s or negedge rst_n_in) 22 begin 23 if(!rst_n_in) 24 begin 25 state<=1'd0; 26 cnt<=0; 27 end 28 else 29 begin 30 state<=state+1'b1; 31 cnt<=cnt+1; 32 if(cnt==8) 33 state<=1'd0; 34 end 35 end 36 //*************************************************************** 37 always@(posedge clk_in) 38 begin 39 case (state) 40 0:begin state<=8'b00000001;end 41 1:begin state<=8'b00000010;end 42 2:begin state<=8'b00000100;end 43 3:begin state<=8'b00001000;end 44 4:begin state<=8'b00010000;end 45 5:begin state<=8'b00100000;end 46 6:begin state<=8'b01000000;end 47 7:begin state<=8'b10000000;end 48 default: begin state<=8'b00000000;end 49 endcase 50 end 51 /****************************************************/ 52 assign led=~state; 53 54 endmodule 55 56 不在电脑前？没关系，QQ手机版让你随时随地接收消息！立刻安装 57 张慢慢 14:35:44 58 module clk_1s 59 ( 60 input clk_in, 61 input rst_n_in, 62 output clk_1s 63 ); 64 65 parameter CLK_PERIOD = 25_000_000; //频率25Mhz 66 67 reg [25:0]cnt; 68 reg pulse; 69 70 assign clk_1s=pulse; 71 72 always@(posedge clk_in or negedge rst_n_in) 73 begin 74 if(!rst_n_in) 75 cnt<=1'b0; 76 else 77 cnt<=cnt+1'b1; 78 if(cnt==(CLK_PERIOD-1)) 79 pulse<=1'b0; 80 if(cnt <(CLK_PERIOD/2)) pulse<=1'b0; 81 else pulse<=1'b1; 82 end 83 endmodule