Verilog HDL Test Bench

As digital systems becomes more complex,it becomes increasingly important to verify the functionality of a design before implementing it in a system,a Test Bench source includes mainly some aspects:

0,set up time scale and operating precision.

 

1,instantiation

 

2,Reg and Wire Declarations

 

3,initial and always(clock,reset)

waring:

 

4,Printing during simulusation

 

5,TASK