. Rolling up the pipeline can optimize the area of pipelined designs with
duplicated logic in the pipeline stages.
. Controls can be used to direct the reuse of logic when the shared logic is
larger than the control logic.
. For compact designs where area is the primary requirement, search for
resources that have similar counterparts in other modules that can be
brought to a global point in the hierarchy and shared between multiple
functional areas.
. An improper reset strategy can create an unnecessarily large design and
inhibit certain area optimizations.
. An optimized FPGA resource will not be used if an incompatible reset is
assigned to it. The function will be implemented with generic elements and
will occupy more area.
//如果需要区域的优化设计，尤其要慎重，针对不同的情况要仔细分析。