FET

How FET got its Name

A voltage applied to the metallic plate modalated the conductance of the underlying semiconductor, which in turn modulated the carrent flowing between ohmic contacts A and B. This phenomenon, where the conductivity of a semiconductor is modulated by an electric field applied normal to the surface of the semiconductor, has been named the field effect.

JFET (Junction FET)

FET
Suppose we connect S to ground, reverse bias at S is VGV_G.

I-V Characteristics

  1. VGV_G = 0. When VD is small, ID is small. Linear I-V. No change in depletion width across channel.
    FET
    FET
  2. VGV_G increases. Channel pinches-off.
    FET
    FET
    FET

Questions

  1. Should/Should not IDI_D = 0 beyond pinch-off?
    No. Carriers can also pass depletion region, but see a much higher resisitance.
  2. Why does VDV_D > VDSatV_D^{Sat} have no effect on ID?
    Increasing VDV_D will also increase the length of pinched-off region. These two effects cancel out.

Pinch-off voltage

VpV_p = Reverse bias between n-channel and p+p^+ gate at the drain end (x=0)(x=0).
h(x)h(x) = Channel half-width at any xx
aa = half width of channel
Assumptions:

  1. Channel with at x=0x=0 decreases uniformly as the reverse bias increases to pinch-off.
  2. VbiV_{bi} neglected.
  3. p+np^+-n gate junction.

Vp=qa2ND2εV_p=\frac{qa^2N_D}{2\varepsilon}
aa: half thickness

Channel Current

LL: length
ZZ: depth
2a2a: thickness

ID=GoVP[VDVP+23(VGVP)3/223(VDVGVP)3/2]I_D=G_oV_P\left[\frac{V_D}{V_P} + \frac23\left(-\frac{V_G}{V_P}\right)^{3/2} - \frac23\left(\frac{V_D-V_G}{V_P}\right)^{3/2}\right]
Go=2aZρLG_o=\frac{2aZ}{\rho L}
ID(sat)=GoVP[VDVP+23(VGVP)3/223]I_D(sat)=G_oV_P\left[\frac{V_D}{V_P} + \frac23\left(-\frac{V_G}{V_P}\right)^{3/2} - \frac23\right]

Gain (Transconductance)

gm(sat)=ID(sat)VG=Go[1(VGVP)1/2]g_m(sat)=\frac{\partial I_D(sat)}{\partial V_G}=G_o\left[1-\left(-\frac{V_G}{V_P}\right)^{1/2}\right]

MESFET (Metal Semiconductor FET)

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Metal-Semiconductor (MS) Contact

FET

Energy Band Diagram of Metal and Semiconductor
  • ΦM\Phi_M: Metal Work Function (the one in photoelectric effect)
  • ΦS\Phi_S: Semiconductor Work Function
  • χ\chi: Electron Affinity. χ=(E0EC)surface\chi=(E_0-E_C)|_{surface}

ΦS=χ+(EcEF)FB\Phi_S=\chi+(E_c-E_F)_{FB}

  • (EcEF)FB(E_c-E_F)_{FB}: Energy difference between EcE_c and EFE_F at flat band (i.e.) zero bias condition.

FET

ΦB=ΦMχ\Phi_B=\Phi_M-\chi

  • ΦB\Phi_B: surface potential-energy barrier encountered by electrons with E=EFE=E_F in the metal.

Schottky Diode

  • ΦM>ΦS\Phi_M>\Phi_S: Applying VA>0V_A>0 lowers EFME_{FM} below EFSE_{FS}, reduces the barrier seen by electrons in the semiconductor.

FET

  • ΦM<ΦS\Phi_M<\Phi_S: Non-rectifying, Ohmic.

FET

Heavily Doped (Degenerately Doped) Semiconductor

FET
When the barrier is thin enough, the carriers can tunnel through.
Upper: forward bias. Below: rev bias
Additional component of current

Schottky Diode Calculations

  • Built-in Voltage

Vbi=1q[ΦB(EcEF)FB]V_{bi}=\frac1q\left[\Phi_B-(E_c-E_F)_{FB}\right]

  • ρ\rho
    • Metal: delta function (charge only on surface)
    • Semiconductor: ρ=qND\rho=qN_D
  • EE:

E(x)=qNDεSi(Wx)0xWE(x)=-\frac{qN_D}{\varepsilon_{Si}}(W-x)\ldots 0\le x\le W

  • VV:

V(x)=qND2εSi(Wx)20xWV(x)=-\frac{qN_D}{2\varepsilon_{Si}}(W-x)^2\ldots 0\le x \le W

  • Depletion Width

W=2εSiqND(VbiVA)W=\sqrt{\frac{2\varepsilon_{Si}}{qN_D}(V_{bi}-V_A)}

  • Φ(x)\Phi(x)

Φ(x)=qNDx22ϵS\Phi(x)=\frac{qN_Dx^2}{2\epsilon_S}

  • Current Density

J=JS(eqVa/kT1)J=J_S(e^{qV_a/kT}-1)
JS=AT2exp(qΦBkT)J_S=A^*T^2\exp\left(-\frac{q\Phi_B}{kT}\right)
AA^* is the Effective Richardson Constant

MOSFET (Metal-Oxide FET)

Composition

  • MOS Capacitor
  • Two pn juncitons

Terminal Naming

  • Carriers enter the structure through Source (S)
  • Leave through the Drain (D)
  • Subject to the control of the Gate (G)

Functionality (NMOS)

  • When VGVTV_G\le V_T, i.e. VGV_G is in accumulation or depletion biased, the gated region contains mostly holes and few electrons, an open circuit is formed.
  • When VG>VTV_G>V_T, i.e. VGV_G is inversion biased, an inversion layer (channel) containing mobile electrons is formed.
  • As VDV_D increases, the channel finally pinches-off, the current saturates.

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MOSFET Pinches-off

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Channel Length Modulation of Short-Channel Device

MOS Energy Band Diagram

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Band Diagram for NMOS
  • Accumulation (VG<0V_G<0) holes accumulate on the semiconductor side of the gate
  • Depletion (0<VG<VT0<V_G<V_T) holes repelled away, leaving Ionized acceptors atoms
  • Inversion (VG>VTV_G>V_T) electron density increase
    • Initially, n<nin<n_i.
    • n=nin=n_i when Ei=EFE_i=E_F
  • When VG=VTV_G=V_T, n=NAn=N_A, the semiconductor seems no longer to be depleted. Instead, it now behave similar to n-type. The channel has formed.

MOS Calculations

ΦS\Phi_S: Surface Potential

ΦS=1q[Ei(bulk)Ei(surface)]\Phi_S=\frac1q[E_i(bulk)-E_i(surface)]

ΦF\Phi_F

ΦF=1q[Ei(bulk)EF]\Phi_F=\frac1q[E_i(bulk)-E_F]
In p-type, NANDN_A\gg N_D, pbulk=niexp([Ei(bulk)EF]/kT)=NAp_{bulk}=n_i\exp([E_i(bulk)-E_F]/kT)= N_A
ΦF=kTqln(NAni)\Phi_F=\frac{kT}{q}\ln\left(\frac{N_A}{n_i}\right)
In n-type, NDNAN_D\gg N_A, nbulk=niexp([EFEi(bulk)])=NDn_{bulk}=n_i\exp([E_F-E_i(bulk)])=N_D
ΦF=kTqln(NDni)\Phi_F=-\frac{kT}{q}\ln\left(\frac{N_D}{n_i}\right)
When VG=VTV_G=V_T,
ΦS=2ΦF\Phi_S=2\Phi_F

Depletion Width WW

Valid before strong inversion:

W=2εSiqNAΦSW=\sqrt{\frac{2\varepsilon_{Si}}{qN_A}\Phi_S}
At strong inversion:

Wm=2ϵkTq2NAln(NAni)W_m=2\sqrt{\frac{\epsilon kT}{q^2N_A}\ln\left(\frac{N_A}{n_i}\right)}
When VG=VTV_G=V_T, ΦS=2ΦF\Phi_S=2\Phi_F, the depletion width
WT=4εSiqNAΦFW_T=\sqrt{\frac{4\varepsilon_{Si}}{qN_A}\Phi_F}

Threshold Voltage VTV_T

For N(-channel)MOS (P-bulk)

VT=2ΦF+ϵOXIDExOϵSi4qNAϵSiΦFV_T=2\Phi_F+\frac{\epsilon_{OXIDE}x_O}{\epsilon_{Si}}\sqrt{\frac{4qN_A}{\epsilon_{Si}}\Phi_F}
For PMOS (N-bulk)
VT=2ΦFϵOXIDExOϵSi4qNDϵSi(ΦF)V_T=2\Phi_F-\frac{\epsilon_{OXIDE}x_O}{\epsilon_{Si}}\sqrt{\frac{4qN_D}{\epsilon_{Si}}(-\Phi_F)}
xOx_O is the thickness of the OXIDE

Cap-Voltage Characteristics

FET

PMOS (n-bulk)

FET

NMOS (p-bulk) a: Low Freq, b&c: Hi Freq

Supplement

JFET pinch-off

FET
Widening everywhere as VSDV_{SD} grows

Why doesn’t current goto 0

If current is 0, the pinch-off will disappear. To maintain pinch-off, a non-zero current must be present.

How does current flow after pinch-off

FET

Gradual Channel Approx

Formula for depetion layer width remainis same at every point and edge of depletion layer is not a multi-valued function at any point

JFET Transconductance

gm=ID(sat)VGg_m=\frac{\partial I_D(sat)}{\partial V_G}
Proportional to VG\sqrt{V_G}
e at every point and edge of depletion layer is not a multi-valued function at any point

JFET Transconductance

gm=ID(sat)VGg_m=\frac{\partial I_D(sat)}{\partial V_G}
Proportional to VG\sqrt{V_G}

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