从机，实现数据读写
module APB_Slave(
input wire PRESETn,
input wire PCLK,
input wire PSELx,
input wire PENABLE,
input wire PWRITE,
input wire [31:0] PADDR,
input wire [31:0] PWDATA,
output reg [31:0] PRDATA
);
reg [31:0] Slave_Data [31:0];
/*
S0: 0x0000_0000 ~ 0x0000_00ff;
S1: 0x0000_0100 ~ 0x0000_01ff;
S2: 0x0000_0200 ~ 0x0000_02ff;
S3: 0x0000_0300 ~ 0x0000_03ff;
*/
wire [5:0] num = PADDR[7:2];
always @(posedge PCLK or negedge PRESETn)
begin
if(!PRESETn) PRDATA <= 32'h00000000;
else
begin
if(PSELx && PENABLE)
begin
if(PWRITE) Slave_Data[num] <= PWDATA;
else PRDATA <= Slave_Data[num];
if(PWRITE) $display("%m Write Addr:%x, Reg:%d, Data:%x", PADDR, num, PWDATA);
else $display("%m Read Addr:%x, Reg:%d, Data:%x", PADDR, num, Slave_Data[num]);
end
end
end // PCLK
endmodule