1.9.SDRAM - 爱码网

SDRAM(soc外接的设备)

Syncronized Dynamic Random Access Memory同步动态随机存取存储器

DDR :SDRAM升级版双倍速的SDRAM

都属于动态内存(相对于SRAM)都要先运行一段初始化代码

NORFLASH\NANDFLASH\硬盘都类似于此

SDRAM通过数据总线和地址总线与SOC通讯

SDRAM数据手册:(给硬件工程师和选型的)

K4T1G164QQ -1Gbit表示128MByte

SDRAM初始化:

原理图:

1.9.SDRAM

S5PV210有两个内存端口

DRAM0->PORT1(最大512M) 实际256MB -0X2FFFFFFF

DRAM1->PORT2(最大1G) 实际256MB -0X4FFFFFFF

NT5TU64M16GG-DDR2-1G-G-R18-Consumer

1.9.SDRAM

128Mb * 8bank 每bank(块)128Mbit

1.9.SDRAM

BA0-BA2:用来选bank(有点像译码器)

通过row address(列地址) + column address(行地址)方式寻址

14位 10位

寻址范围 = 2^14 +2^10 =2^24=16MB=128Mb

-S

初始化:步骤看S5PV210 UM 和soc中DDR控制器\ddr芯片有关

初始化SDRAM0
初始化SDRAM1

To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.

2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL.

3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.

4. Set the PhyControl0.ctrl_start bit-field to ‘1’.

5. Set the ConControl. At this moment, an auto refresh counter should be off.

6. Set the MemControl. At this moment, all power down modes should be off.

7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.

8. Set the PrechConfig and PwrdnConfig registers.

9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC

parameters.

10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.

11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked.

12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.

13. Confirm whether stable clock is issued minimum 200us after power on

14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level. 1-5 S5PV210_UM 1 DRAM CONTROLLER

15. Wait for minimum 400ns.

16. Issue a PALL command using the DirectCmd register.

17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.

18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.

19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.

20. Issue a MRS command using the DirectCmd register to reset the memory DLL.

21. Issue a PALL command using the DirectCmd register.

22. Issue two Auto Refresh commands using the DirectCmd register.

23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.

24. Wait for minimum 200 clock cycles.

25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.

26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.

27. Set the ConControl to turn on an auto refresh counter.

28. If power down modes is required, set the MemControl registers.

1. 为了给控制器和存储设备提供稳定的电源，控制器必须对一个逻辑进行断言并保持CKE

低的水平。然后使用稳定的时钟。注意:XDDR2SEL应该是高水平，以保持低的CKE。

2. 设置PhyControl0。ctrl_start_point PhyControl0。ctrl_inc位字段根据时钟修正值

频率。设置PhyControl0。ctrl_dll_on位域为“1”以打开PHY DLL。

3.DQS清洗:设置PhyControl1。ctrl_shiftc PhyControl1。ctrl_offsetc位字段来纠正值根据时钟频率和内存tAC参数。

4. 设置PhyControl0。ctrl_start位字段到' 1 '。

5. 设置ConControl。此时，应该关闭自动刷新计数器。

6. 设置MemControl。此时，所有关机模式应该关闭。

7. 设置MemConfig0寄存器。如果有两个外部内存芯片，则设置MemConfig1寄存器。

8. 设置PrechConfig和PwrdnConfig寄存器。

9. 根据内存AC设置TimingAref、TimingRow、TimingData和TimingPower寄存器

参数。

10. 如果需要QoS方案，则设置QosControl0~15和QosConfig0~15寄存器。

11. 1 .等待疾病的发展ctrl_locked位字段更改为' 1 '。检查PHY DLL是否被锁定。

12. PHY动态链接库补偿了进程、电压和温度(PVT)引起的延迟量变化。

内存操作期间的变化。因此，为了可靠运行，PHY DLL不应该关闭。可以关闭

只是运行频率较低。如果使用off模式，则设置PhyControl0。ctrl_force位字段来纠正值

根据病情。ctrl_lock_value[9:2]位字段来修正延迟量。清除

PhyControl0。ctrl_dll_on位域关闭PHY DLL。

13. 确认开机后稳定时钟是否发出最小200us

14. 使用DirectCmd寄存器发出一个NOP命令来断言并将CKE保持在一个逻辑高位。

1 - 5

1 DRAM控制器

15. 等待最少400ns。

16. 使用DirectCmd寄存器发出一个PALL命令。

17. 使用DirectCmd寄存器发出EMRS2命令来对操作参数进行编程。

18. 使用DirectCmd寄存器发出EMRS3命令来对操作参数进行编程。

19. 使用DirectCmd寄存器发出EMRS命令来启用内存dll。

20.使用DirectCmd寄存器发出MRS命令来重置内存DLL。

21. 使用DirectCmd寄存器发出一个PALL命令。

22. 使用DirectCmd寄存器发出两个自动刷新命令。

23. 使用DirectCmd寄存器发出MRS命令来对操作参数进行编程，而不需要重新设置

内存DLL。

24. 等待至少200个时钟周期。

25. 使用DirectCmd寄存器发出EMRS命令来对操作参数进行编程。如果强迫症

不使用校准，发出EMRS命令来设置OCD校准默认值。之后，发出电子邮件命令退出OCD校准模式，并对操作参数进行编程。

26. 如果有两个外部存储芯片，对chip1内存设备执行步骤14~25。

27. 将ConControl设置为打开自动刷新计数器。28. 如果需要关机模式，请设置

MemControl寄存器。

Start.S添加了

//初始化SDRAM

bl sdram_asm_init

此函数在sdram_init.S实现

代码:

1.9.SDRAM

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