A signal is sent by a transmitter along a transmission line and delivered to a receiver.
The receiver resolve the value of the signal transmitted within valid timing windows determined by the synchronization mechanism.
The signal should then be removed from the transmission line by a resistive element, labelled as the terminator, so that it does not interfere with the transmission and reception of subsequent signals.
Serial termination reduces signal ringing at the cost of reduced signal swing, and is used at the receiver.
Parallel termination improves signal quality but consumes additional active power to remove the signal form the transmission line. Parallel termination is used at the transmitter in modern high-speed memory systems.
Fig.2 shows the series stub termination scheme used in DDR SDRAM memory systems. The series resistor is designed to increase the damping ratio and to proved an artificial impedance discontinuity that isolates the complex impedances within the DRAM package, resulting in the reduction of signal reflections back onto the PCB trace from within the DRAM device package.
The design in Fig.2 means that the burden is placed on system design engineers to add termination resisteors to the DRAM memory syste. In DDR2 and DDR3 SDRAM devices, the use of higher cost Fin Ball Grid Array(FBGA) package enables DRAM device manufacturers to remove part of the inductance that exists in the input pins of SOI and TSOP packages. As a result, DDR2 and DDR3 SDRAM devices could then adopt an on die termination scheme that more closely represents the ideal temination scheme in Fig.1.
Fig.3 shows that in DDR2 devices, depending on the programmed state of the control register and the value of the on-die-termination signal, switches SW1 and SW2 can be controlled independently to provied different termination values as needed.