MT8167芯片 TDM Design notice V1
TDM ADC(CODEC) vs MTK TDM IN Design notice
TDM design flow chart
- MTK provide a flow to design the TDM audio system.
Model -DI from Falling edge
- Collect the Tbsdd(ADC output DI from BCK falling edge delay time) and Ttrace(PCB trace delay).
- fBCK is the audio serial data clock rate.
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Model -DI from Rising edge
- Collect the Tbsdd(ADC output DI from BCK rising edge delay time) and (PCB trace delay).
- fBCK is the audio serial data clock rate.
- Calculate the maximum Tbsdd value as attachment .
HW workaround -Non inverse mode
- Due to ADC DI delay time too long to strobe effective data window ,therefore change BCK to non this mode the tLRB & tBLR(LRCK edge to BCK rising edge time) can's meets ADC converter's requirement.(example: AKM5558 tLRB = tBLR= 14ns)
- Base on Non-inverse mode: Add the Inverter + D-FF design delay LRCK half T to meet tBLR & tLRB requirement.