verilog实现异步(双口)RAM

在异步FIFO的应用中所用的存储器一般都是RAM，所以异步的RAM对于异步FIFO实现是基础的

module asyn_ram
#(parameter DWIDTH=4,//data width
				AWIDTH=10)//address width 
(
	input wr_clk,
	input[DWIDTH-1:0] wr_data,
	input wr_en,
	input[AWIDTH-1:0] wr_addr,
	
	input  rd_clk,
	output [DWIDTH-1:0] rd_data,
	input  rd_en,
	input[AWIDTH-1:0] rd_addr
);

reg[DWIDTH-1:0] rw_mem [2**AWIDTH-1:0];//define the memory
reg[AWIDTH-1:0] raddr;
always@(posedge wr_clk )
begin
	if(wr_en) begin
		rw_mem[wr_addr]<=wr_data;
	end
end

always@(posedge rd_clk)
begin
	if(rd_en) begin
		raddr<=rd_addr;
	end
end
assign rd_data=rw_mem[raddr];
endmodule 

在quartus中综合后的technology map viewer是这样的：

用modelsim仿真代码为：

`timescale 1ns/1ns
module asyn_ram_tb();

	reg wr_clk;
	reg[3:0] wr_data;
	reg wr_en;
	reg[9:0] wr_addr;
	
	reg  rd_clk;
	wire [3:0] rd_data;
	reg  rd_en;
	reg[9:0] rd_addr;
	
asyn_ram u1(
	.wr_clk(wr_clk),
	.wr_data(wr_data),
	.wr_en(wr_en),
	.wr_addr(wr_addr),
	.rd_clk(rd_clk),
	.rd_data(rd_data),
	.rd_en(rd_en),
	.rd_addr(rd_addr)
);

initial begin
	wr_clk=1'b0;
	wr_en=1'b0;
	forever #5 wr_clk=~wr_clk;
end

initial begin
	rd_clk=1'b0;
	rd_en=1'b0;
	forever #8 rd_clk=~rd_clk;
end

always begin
	#15 wr_en=1'b1;
		 wr_addr=4'd0;
		 wr_data=4'd1;
	#10 wr_addr=4'd1;wr_data=4'd2;
	#10 wr_addr=4'd2;wr_data=4'd3;
	#10 wr_addr=4'd3;wr_data=4'd4;
	#10 wr_addr=4'd4;wr_data=4'd5;

end
always begin
	#40 rd_en=1'b1;
		 rd_addr=4'd0;
	#16 rd_addr=4'd1;
	#16 rd_addr=4'd2;
	#16 rd_addr=4'd3;
	#16 rd_addr=4'd4;
	$stop;
end

endmodule

仿真波形如下：