Quartus Signal Tap II Debugging

working environment:

Linux

Steps

1. Open RTL project:
   open quartus under Linux:
   quartus
   open project file (file that ends with .qpt)
2. Signal tap II
   Tool -> singal Tap II
   
3. Adding clock
   signal configuration -> name:clock -> filter: Signal Tap II Pre-synthesis -> list
4. Adding signal that you want to test
   double click in the window, adding signals and hit ok
   filter: pre synthesis
5. Hit save, xxx.stp file will be generated
6. Synthesizing the project, generating bit file “.sof”
7. export your bit file to FPGA
8. open signal Tap II analyzer
9. Hit “hardware” to connect to your JTAG
10. Prob the posdege of the signal that you want to trigger the test
11. Running the program on FPGA and start analyzing