《Digital Integrated Circuits》读后笔记(二)

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chapter 5 The CMOS Inverter

1. inverter gate

• cost
• static behavior
• dynamic response
• energy and power consumption

2. The Static CMOS inverter

MOS: when $|V_{GS}<V_{T}|$∣VGS​<VT​∣ , the off-resistance is infinite

​ when $|V_{GS}>V_{T}|$∣VGS​>VT​∣ , the on-resistance is finite

Ideal Features:

• when $V_{in}$Vin​ is high, NMOS is on, PMOS is off. $V_{out}$Vout​ is 0.

  when $V_{in}$Vin​ is low, NMOS is off, PMOS is on. $V_{out}$Vout​ is $V_{DD}$VDD​.

  Swing is from $V_{DD}$VDD​ and $GND$GND . logic level is not dependent upon the relative device sizes.

• steady state: finite resistance between output and $V_{DD}$VDD​ or $GND$GND . No current flow, no static power.

• input resistance is extremely high. Theoretically, inverter can have an infinite fan-out.

  However, increasing fan-out will increase the propagation delay.

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VTC(voltage-transfer characteristic):

a narrow transition zone.

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Transient behavior:

output capacitance of the gate, $C_L$CL​

composed of drain diffusion capacitances of NMOS and PMOS transistors, the capacitance of the connecting wires, the input capacitance of fan-out gates.

response time: time constant $R_pC_L$Rp​CL​.

Conclusion: A fast gate is built by keeping the output capacitance small or by decreasing the on-resistance of the transistor.

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Robustness: static CMOS converter is insensitive to these variations

3. The switching threshold of CMOS inverter $V_M$VM​

noise margin $V_{IH}$VIH​ and $V_{IL}$VIL​

switching threshold $V_M$VM​ is defined as the point where $V_{in} = V_{out}$Vin​=Vout​.

Supposed the supply voltage is high and the velocity-saturated appear:

$V_{M} = \frac{rV_{DD}}{1+r}$VM​=1+rrVDD​​ ($V_{DD}$VDD​ is high) $r = \frac{k_pV_{DSATp}}{k_nV_{DSATn}} = \frac{\upsilon_{satp}W_p}{\upsilon_{satn}W_n}$r=kn​VDSATn​kp​VDSATp​​=υsatn​Wn​υsatp​Wp​​

if $V_M$VM​ located at mid, $r = 1$r=1, and $(W/L)_p = (W/L)_n\times (V_{DSATn}k_n^{’}/V_{DSATp}k_p^{'})$(W/L)p​=(W/L)n​×(VDSATn​kn’​/VDSATp​kp′​)

if $V_M$VM​ is required high, then $r>1$r>1, make PMOS wider

Analysis:

• $V_M$VM​ - $W_p/W_n$Wp​/Wn​ : $V_M$VM​ is insensitive to the ratio. So we can set the width of the PMOS transistor to values smaller than those required for symmetry.
• If required asymmetrical transfer characteristics, then we can change the ratio.

4. Noise margin $NM_H$NMH​and $NM_L$NML​:

$V_{IH}$VIH​ and $V_{IL}$VIL​ :operational points of the inverter where $\frac {dV_{out}}{dV_{in}} = -1$dVin​dVout​​=−1. $g = -1$g=−1.

$g = \frac{1+r}{(V_M-V_{Tn}-V_{DSATn}/2)(\lambda_n-\lambda_p)}$g=(VM​−VTn​−VDSATn​/2)(λn​−λp​)1+r​ $g$g is determined by channel length modulation.

5. Scaling the supply voltage

$g$g is inverse ratio with $V_M$VM​. And $V_M$VM​ is proportional with $V_{DD}$VDD​ if $r$r is fixed.

So if $g$g increases when $V_{DD}$VDD​ decreases.(Supposed)

However:

• reducing the supply voltage is detrimental to the performance on the gate.
• dc-characteristic becomes increasingly sensitive to variations in the device parameters such as transistor threshold when supply voltage is comparable with threshold.
• reducing the signal swing. More sensitive to external noise.

Examples:

At around 100 mV, gain in transition-region approaches 1. And VTC is detoriated.

Conclusion:

$V_{DDmin}>2...4\phi_T$VDDmin​>2...4ϕT​ , if we want a low $V_{DD}$VDD​, we need to reduce the temperature.

If $V_{DD}$VDD​ is under threshold, $g = -(\frac{1}{n})(e^{V_{DD}/2\phi_T}-1)$g=−(n1​)(eVDD​/2ϕT​−1).

6. The Dynamic behavior

* Only here we discuss the dynamic behavior

Capacitances:

Supposed $V_{in}$Vin​ has an ideal input voltage source.

• Gate-Drain Capacitance $C_{gd12}$Cgd12​

  during the first half, $M1$M1 is cut-off or saturation mode. The channel capacitance does not play a role here. If cut-off, it is between gate and bulk, if saturation, it is between gate and source. The capacitance is mainly the overlap capacitance.

  Miller effect the capacitance-to-ground must have a value that is twice as large as the floating capacitance.

  $C_{gd} = 2C_{GD0}W$Cgd​=2CGD0​W $C_{GD0}$CGD0​ is the overlap capacitance per unit width

• Diffusion Capacitance $C_{db1}$Cdb1​ and $C_{db2}$Cdb2​

  the capacitance between drain and bulk.

• Wiring Capacitance $C_w$Cw​

  connecting wires

• Gate Capacitance $C_{g3}$Cg3​ and $C_{g4}$Cg4​

  fanout capacitance $C_{fanout} = C_{gate}(NMOS) + C_{gate}(PMOS)=$Cfanout​=Cgate​(NMOS)+Cgate​(PMOS)=

  $(C_{GSOn}+C_{GDOn}+W_nL_nC_{ox})+(C_{GSOp}+C_{GDOp}+W_pL_pC_{ox})$(CGSOn​+CGDOn​+Wn​Ln​Cox​)+(CGSOp​+CGDOp​+Wp​Lp​Cox​)

  The total channel capacitance is not constant actually. varies from $2/3WLC_{ox}$2/3WLCox​ to the full $WLC_{ox}$WLCox​.

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Propagation Delay :

$t_p = \displaystyle \int^{v_2}_{v_1}{\frac{C_L(x)}{i(v)}dv}$tp​=∫v1​v2​​i(v)CL​(x)​dv

$R_{eq} = {\frac{3}{4}}{\frac{V_{DD}}{I_{DSAT}}}(1-{\frac{7}{9}}\lambda V_{DD})$Req​=43​IDSAT​VDD​​(1−97​λVDD​) $R_{eq}$Req​ is the average on-resistance of the MOS transistor.

$t_{pHL}=In(2)R_{eqn}C_{L}=0.69R_{eqn}C_{L}$tpHL​=In(2)Reqn​CL​=0.69Reqn​CL​

$t_{pLH} = 0.69R_{eqp}C_L$tpLH​=0.69Reqp​CL​

$t_p = (t_{pHL}+t_{pLH})/2=0.69C_L(R_{eqn}+R_{eqp})/2$tp​=(tpHL​+tpLH​)/2=0.69CL​(Reqn​+Reqp​)/2

$R_{eqn}$Reqn​ and $R_{eqp}$Reqp​ is the normalized on-resistances. $(\frac{W}{L})$(LW​) is ratio. the realistic resistance is $R_{eqn}/(W/L)$Reqn​/(W/L).

If we want $R_{eqn}==R_{eqp}$Reqn​==Reqp​ , then PMOS is wider than NMOS. However, $t_{pHL}=t_{pLH}$tpHL​=tpLH​ does not mean $t_p$tp​ is smallest. We can make PMOS smaller than computation

Another computation: ignore the factor $\lambda$λ

$t_{pHL}={\frac{3}{4}}{\frac{V_{DD}}{I_{DSATn}}}\approx0.52\frac{C_L}{(W/L)_n(k_n)^{’}V_{DSATn}}$tpHL​=43​IDSATn​VDD​​≈0.52(W/L)n​(kn​)’VDSATn​CL​​

If $V_{DD}$VDD​ decreases, $t_{pHL}$tpHL​ will increases.

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Conclusion:

• Reduce $C_L$CL​

• Increase the (W/L) ratio

• Increase $V_{DD}$VDD​

7）Design for Performance

Supposed symmetrical inverter:

$C_L=C_{int}+C_{ext}$CL​=Cint​+Cext​

$t_p=0.69R_{eq}(C_{int}+C_{ext})=0.69R_{eq}C_{int}(1+C_{ext}/C_{int})=t_{p0}(1+C_{ext}/C_{int})$tp​=0.69Req​(Cint​+Cext​)=0.69Req​Cint​(1+Cext​/Cint​)=tp0​(1+Cext​/Cint​)

$t_{p0}$tp0​ is unloaded delay

$C_{int}=SC_{iref}$Cint​=SCiref​ $R_{eq}=R_{ref}/S$Req​=Rref​/S $S$S is the sizing factor. $C_{iref}$Ciref​ is a minimize-sized inverter.

$t_p = 0.69R_{iref}C_{iref}(1+\frac{C_{ext}}{SC_{iref}})=t_{p0}(1+\frac{C_{ext}}{SC_{iref}})$tp​=0.69Riref​Ciref​(1+SCiref​Cext​​)=tp0​(1+SCiref​Cext​​)

Conclusion:

if $S$S is larger, $t_p$tp​ is smaller.

8. A Chain of Inverter

$C_{int}=\gamma C_{g}$Cint​=γCg​ $\gamma$γ is a proportionality factor. close to 1.

$t_p=t_{p0}(1+\frac{C_{ext}}{rC_g})=t_{p0}(1+f/\gamma)$tp​=tp0​(1+rCg​Cext​​)=tp0​(1+f/γ) $f$f is effective fanout.

$t_{p,j}=t_{p0}(1+\frac{C_{g,j+1}}{\gamma C_{g,j}})=t_{p0}(1+\frac{f_j}{\gamma})$tp,j​=tp0​(1+γCg,j​Cg,j+1​​)=tp0​(1+γfj​​)

$t_p=\displaystyle \sum^{N}_{j=0}t_{p,j}=t_{p0}\displaystyle \sum^{N}_{j=0}(1+\frac{C_{g,j+1}}{\gamma C_{g,j}})$tp​=j=0∑N​tp,j​=tp0​j=0∑N​(1+γCg,j​Cg,j+1​​) $C_{g,N+1}=C_L$Cg,N+1​=CL​

To make $t_p$tp​ min, we need each inverter is sized up by the same factor $f$f.

$f=\sqrt[N]{C_L/C_{g,1}}=\sqrt[N]{F}$f=NCL​/Cg,1​​=NF​ $t_p=Nt_{p0}(1+\sqrt[N]{F}/\gamma)$tp​=Ntp0​(1+NF​/γ)

The optimized $f$f:

if $\gamma$γ equals 1, $f$f is chose to be 3.6.If $f$f is too small, which means $N$N is too large, then $t_p$tp​ will be larger.

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If the input signal changes gradually, PMOS and NMOS conduct simultaneously.

$t_s$ts​-$t_p$tp​: $t_p$tp​ increases linearly with $t_s$ts​

So we can change $t_p$tp​ : ${t_p}^{i}={t_{step}}^{i}+\eta {t_{step}}^{i-1}$tp​i=tstep​i+ηtstep​i−1

8. Dynamic Power Consumption:

$E_{VDD}=C_L{V_{DD}}^{2}$EVDD​=CL​VDD​2

$E_{out}=\frac{C_L{V_{DD}}^{2}}{2}$Eout​=2CL​VDD​2​

Half energy has been dissipated by PMOS

Conclusion: $E_{dissipated} = C_L{V_{DD}}^{2}$Edissipated​=CL​VDD​2

$P_{dyn} = C_L{V_{DD}}^{2}f_{0->1}$Pdyn​=CL​VDD​2f0−>1​ $f_{0->1} = 2t_p$f0−>1​=2tp​ means a switched time.(on and off)

However:

switching factor $f_{0->1}$f0−>1​ $P_{dyn}=C_L{V_{DD}}^{2}P_{0->1}f=C_{EFF}{V_{DD}}^{2}f$Pdyn​=CL​VDD​2P0−>1​f=CEFF​VDD​2f $f$f is clock time

$C_{EFF}$CEFF​ effective capacitance

Solution: How to reduce power

• Reducing $V_{DD}$VDD​ But $V_{DD}$VDD​ need to be larger than 2$V_{T}$VT​, or the performance is bad.
• Reducing the effective capacitance

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Analysis:

$t_p=t_{p0}((1+f/\gamma)+(1+F/f\gamma))$tp​=tp0​((1+f/γ)+(1+F/fγ))

$t_{p0}$tp0​~$\frac{V_{DD}}{V_{DD}-V_{TE}}$VDD​−VTE​VDD​​

$V_{TE} = V_{t}+V_{DSATn}/2$VTE​=Vt​+VDSATn​/2

Conclusion: Energy & Performance

if $F$F is larger, the optimal sizing factor for energy is smaller than the one for performance.

9. Direct-Path Currents

$E_{dp}=V_{DD}\frac{I_{peak}t_{sc}}{2}+V_{DD}\frac{I_{peak}t_{sc}}{2}=t_{sc}V_{DD}I_{peak}$Edp​=VDD​2Ipeak​tsc​​+VDD​2Ipeak​tsc​​=tsc​VDD​Ipeak​

$P_{dp}=t_{sc}V_{DD}I_{peak}f=C_{sc}{V_{DD}}^{2}f$Pdp​=tsc​VDD​Ipeak​f=Csc​VDD​2f

$t_{sc}=\frac{V_{DD}-2V_{T}}{V_{DD}}t_{s}$tsc​=VDD​VDD​−2VT​​ts​

$t_{sc}$tsc​ represents the time both devices are conducting.

$t_s$ts​ represents the 0-100% transition time.

If we want to decrease the direct-path dissipation, we need to make $t_p$tp​ larger.

10. Static consumption

$P_{stat} = I_{stat}V_{DD}$Pstat​=Istat​VDD​ $I_{stat}$Istat​ is a leakage current

• subtheshold current solution: SOI
• drain leakage current

11. Put it all together

$P_{tot} = P_{dyn}+P_{dp}+P_{stat}$Ptot​=Pdyn​+Pdp​+Pstat​

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PDP power-delay product: $PDP=P_{av}t_p$PDP=Pav​tp​ average energy consumed per switching event

$PDP = C_L{V_{DD}}^{2}f_{max}t_{p}=\frac{C_L{V_{DD}}^{2}}{2}$PDP=CL​VDD​2fmax​tp​=2CL​VDD​2​

switching event means 0->1 or 1->0 transition

$E_{av}$Eav​ is twice the PDP

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EDP energy-delay product: combine a measure of performance and energy

$EDP = \frac{C_L{V_{DD}}^{2}}{2}t_p$EDP=2CL​VDD​2​tp​

High supply voltage reduce delay, but harm the energy

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Conclusion:

$V_{DDopt}=\frac {3}{2} V_{TE}$VDDopt​=23​VTE​

12. Scaling technology

The interconnect component