Rapid IO
结构
logical layer：protocols，packet formats，header，payload
transport layer：route packet
physical layer（built-in PLL clock-recovery）：interface information 1X/4X
Peripheral data flow：Without interrupt to the CPU
Clock：Rx clock match Tx clock
SRIO transactions: request and response packet(packet match)
SRIO packet types: decided by FType and TType;max payload(256 B)
Communicatiion Model: Direct I/O operaton / Message passing
Direct I/O operation： a local table of addresses for dest device (insert in packet header, dest peripheral extract) 需要知道目的设备的地址，LSU配合MAU, 8 LSU，每个LSU包含7个Regs
Message passing：不需要知道目的设备的内存映射，有序，TXU 配合 RXU 加doorbell，通过mail信息：mailbox identifier >> dst memory。 Response 有着最高系统优先级。
data is transfered from the shadow registers to the actual LSU registers.
shadow register: copy of LSU_Reg0-5, LSU_Reg 6 is shared.
packet head information descriptors: point to data buffer in memory.
FlowId: identify buffer and descriptor queue; be used for storing the payload
Message: TX: Type 11/ Type 9
Type11: gets a response packet with outgoing message segment/release the descriptor
Type 9: no response
in order delivery: use the same mailbox and letter combination between two endpoints using the same device IDs.
Peripheral ID Resgister(PID): constant、ID、ID-Version、read-only
maintenance：type 8 packets(no address, write req, read response) >> capability(CARS), command and status(CSRs)
Direct I/O(Doorbell) serving interrupt: generated from any 1X port to any of the internal cores.
transfer information descriptor(TID) >> Block(A,B,C,D…) // circular buffer approach
message passing servicing interrupt: CPPI DMA >> transfer data to destination
CPPI queue: store packets // linklist approach.