第一步:画出原理图

第二步,将画出的原理图利用硬件语言实现
module fsm_cola_ctrl(
input wire sclk,
input wire rst_n,
input wire [1:0]pi_money,
output reg po_cola,
output reg po_money
);
reg [4:0] state;
parameter IDLE =5'b00001;
parameter HALF =5'b00010;
parameter ONE =5'b00100;
parameter ONE_HALF =5'b01000;
parameter TWO =5'b10000;
[email protected](posedge sclk or negedge rst_n)
if(!rst_n)
state<=IDLE;
else case(state)
IDLE: if(pi_money == 2'b01)
state <= HALF;
else if(pi_money == 2'b10)
state<=ONE;
else state <= IDLE;
HALF: if(pi_money == 2'b01)
state<=ONE;
else if(pi_money == 2'b10)
state <= ONE_HALF;
else state <= IDLE;
ONE: if(pi_money == 2'b01)
state <= ONE_HALF;
else if(pi_money == 2'b10)
state <= TWO;
else state<=IDLE;
ONE_HALF: if(pi_money == 2'b01)
state<=TWO;
else if(pi_money == 2'b10)
state <= IDLE; //不找零 出可乐
else state<=ONE_HALF;
TWO: if(pi_money == 2'b01)
state<=IDLE; //不找零 出可乐
else if(pi_money == 2'b10)
state<=IDLE; //找零 出可乐
else state<=TWO;
default:state<=IDLE;
endcase
[email protected](posedge sclk or negedge rst_n)
if(!rst_n)
po_cola<=1'b0;
else if(state == ONE_HALF&&pi_money == 2'b10)
po_cola<=1'b1;
else if(state == TWO && pi_money == 2'b01)
po_cola<=1'b1;
else if(state==TWO&&pi_money == 2'b10)
po_cola<=1'b1;
else
po_cola<=1'b0; //当时我将找零跟出可乐写到同一个模块当中,导致编译通过测试显示高阻态
[email protected](posedge sclk or negedge rst_n)
if(!rst_n)
po_money<=1'b0;
else if(state == TWO&&pi_money == 2'b10)
po_money<=1'b1;
else po_money<=1'b0;
endmodule
第三步,写测试模块
`timescale 1ns/1ns
module tb_fsm_cola();
reg sclk;
reg rst_n;
reg [1:0]pi_money;
wire po_cola;
wire po_money;
initial
begin
sclk=0;
rst_n=0;
pi_money=0;
#20
rst_n=1;
end
always # 10 sclk=~sclk;
always # 50 pi_money={$random}%3;
fsm_cola_ctrl fsm_cola_ctrl_inst(
.sclk (sclk ),
.rst_n (rst_n ),
.pi_money (pi_money ),
.po_cola (po_cola ),
. po_money ( po_money )
);
endmodule
第四步,将仿真图像P出来
