编译好Verilog文件后（module名与文件名一致）
点击Processing 》Start 》Start Test Bench Template Writer创建testbench的.vt文件
自动保存在工程目录下的simulation/modelsim文件夹下，打开编辑
`timescale 1 ps/ 1 ps
module kechengsheji_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg A;
reg B;
reg C;
reg D;
reg E;
// wires
wire L;
wire W;
// assign statements (if any)
kechengsheji i1 (
// port map - connection between master ports and signals/registers
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.L(L),
.W(W)
);
initial
begin
// code that executes only once
// insert code here --> begin
A = 0;
B = 0;
C = 0;
D = 0;
E = 0;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 1;
E = 1;
#100 A = 1;
B = 0;
C = 1;
D = 0;
E = 1;
#100 A = 1;
B = 0;
C = 1;
D = 0;
E = 0;
#100 A = 0;
B = 1;
C = 1;
D = 0;
E = 1;
#100 A = 1;
B = 1;
C = 1;
D = 1;
E = 1;
@eachvec;
// --> end
end
endmodule
eachvec可以删除
一定要在
initial
begin// code that executes only once
// insert code here --> begin
中初始化输入信号
点击Assignments》Setting…
点击Test Benches 输入test bench name，保持和testbench.vt中的module后面的一致，这个界面可以设置初始执行时间。
点击“…”浏览vt文件，点击add
ok，ok，ok。
开始仿真：
Tools》Run EDA Simulation Tool》EDA RTL Simulation