生成 VHDL 双端口 RAM 意外锁存器

Question

我为我的 16 位 MIPS 架构编写了一个寄存器文件，在这里我确保我的 register0 包含全零，没有语法错误但我有一些问题

1. 我是否正确地进行了类型转换？因为我收到了一些关于正在生成闩锁的警告。我在这里做错了什么？

2. 还有 conv_integer 和 to_integer(unsigned((w_addr)) 有什么区别？因为当我使用 to_integer(unsigned(r_addr1)=0) 时遇到错误。

   library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use IEEE.std_logic_unsigned.all;
   use IEEE.NUMERIC_STD.ALL;
   
   
   entity regfile is
   generic(
   N: integer:=4; --number of bits for address
   W: integer:=16 --number of bits
   );
    Port ( clk : in  STD_LOGIC;
      w_en : in  STD_LOGIC;
      r_addr1,r_addr2,w_addr : in  STD_LOGIC_VECTOR (N-1 downto 0);
      w_data: in STD_LOGIC_VECTOR (W-1 downto 0);
         r_data1, r_data2  : out  STD_LOGIC_VECTOR (W-1 downto 0));
   end regfile;
   
      architecture Behavioral of regfile is
      type regfile_type is array (W-1 downto 0) of STD_LOGIC_VECTOR (W-1 downto 0);
      signal RegisterFile: regfile_type;
      begin
      process(clk)
      begin
   if (clk = '1') then
       if (w_en = '1') then
           RegisterFile(to_integer(unsigned(w_addr))) <= w_data;
       end if;
   end if;
     end process;
        process (r_addr1, r_addr2)     
   begin
       if (conv_integer(r_addr1)=0) then
           r_data1 <= X"0000";
               else r_data1<=RegisterFile(to_integer(unsigned(r_addr1)));
       end if;
       if (conv_integer(r_addr2)=0) then 
           r_data2 <= X"0000";
               else r_data2 <= RegisterFile(to_integer(unsigned(r_addr2)));
       end if;
      end process;
       end Behavioral;
   

这些是我收到的警告

WARNING:Xst:819 - "E:/Xilinx Projects/regfile/regfile.vhd" line 49: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:<w_en>, <w_data>
WARNING:Xst:819 - "E:/Xilinx Projects/regfile/regfile.vhd" line 58: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <RegisterFile>
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <RegisterFile_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

Answer 1

1.行：

if (clk = '1') then

应该是：

if (clk'event and clk = '1') then

或：

if rising_edge(clk) then

这是创建闩锁的地方。虽然敏感度列表似乎应该隐含该事件，但它需要明确，综合工具才能正确推断触发器。

2. to_integer(unsigned(r_addr1)=0) - 你的意思是to_integer(unsigned(r_addr1))=0（应该可以正常工作）？小心匹配你的括号。顺便说一句，unsigned 与整数文字相比很好，所以你不需要 to_integer 这里。只需unsigned(r_addr1)=0 即可。

Answer 2

您的时钟进程未正确写入。这些工具没有意识到 clk 实际上是一个时钟。您需要使用 clk'event 或更好的是使用rising_edge()。这些工具正在创建一个组合过程，而不是一个顺序过程。由于 if 语句中没有 else 条件，它使您的 RegisterFile 成为一个锁存器。这里有更多关于what is a latch and how to avoid latches in your FPGA的信息

process(clk)
begin
  if rising_edge(clk) then
    if w_en = '1' then
      RegisterFile(to_integer(unsigned(w_addr))) <= w_data;
    end if;
  end if;
end process;