【发布时间】:2021-03-02 18:18:30
【问题描述】:
我正在尝试编写一个 5 位 Mealy 奇偶校验检查器。除了对 5 位输出进行检查的部分之外,我编写了一些代码(复位、下一个状态逻辑和输出逻辑)。如果 1'b1 的个数是奇数,如何检查 5 位变量?
module parity(clk, rst, w,z);
input clk, rst, w;
reg [1:0] present, next;
output reg z;
parameter s0 = 4'b0000, s1 = 4'b0001, s2 = 4'b0010, s3 = 4'b0011, s4 = 4'b0100, s5 = 4'b0101, s6 = 4'b0110, s7 = 4'b0111, s8 = 4'b1000, s9 = 4'b1001, s10 = 4'b1010;
//Reset
always @(posedge clk, posedge rst)
begin
if(rst)
present <= s0;
else
present <= next;
end
//Next State logic
always @(present, w)
begin
case(present)
s0: if(~w) next = s1; else next = s2;
s1: if(~w) next = s3; else next = s4;
s2: if(~w) next = s4; else next = s3;
s3: if(~w) next = s5; else next = s6;
s4: if(~w) next = s6; else next = s5;
s5: if(~w) next = s7; else next = s8;
s6: if(~w) next = s8; else next = s7;
s7: if(~w) next = s9; else next = s10;
s8: if(~w) next = s10; else next = s9;
s9: if(~w) next = s0; else next = s0;
s10: if(~w) next = s0; else next = s0;
default: next = s0;
endcase
end
always @(w, present)
begin
if (present == s10 && w == 1)
z = 1'b1;
else
z = 1'b0;
end
endmodule
【问题讨论】:
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请注意,您在此设计中的任何地方都没有 5 位信号。