信号下降到未定义，而所有相关信号都已定义

Question

我正在编写一个必须查找每个传入位的过程，跟踪接收到的位的总数是否为 1，并且到时候必须将值与参考值进行比较。流程如下：

parity_tester : process(clk, sub_rst, barrel_data_in, barrel_enable, parity_test, parity_ref)
        variable last_known_enable      : boolean := false;
        variable last_known_data        : STD_LOGIC := '0';
        variable parity_error_out       : STD_LOGIC := '0';
        variable parity_ref_reg         : STD_LOGIC := '0';
        variable even                   : STD_LOGIC := '1';
    begin
        if sub_rst then
            last_known_enable   := false;
            last_known_data     := '0';
            parity_error_out    := '0';
            even                := '1';
        elsif rising_edge(clk) then
            if barrel_enable then
                last_known_enable   := true;
                last_known_data     :=  barrel_data_in;
            else
                if last_known_enable then
                    last_known_enable := false;
                    if last_known_data = '1' then
                        even := not even;
                    end if;
                end if;
            end if;

            if parity_test then
                case parity_bit_in_type is
                    when 0 =>
                        parity_error_out := even xnor parity_ref;
                    when 1 =>
                        parity_error_out := even xor parity_ref;
                    when 2 =>
                        parity_error_out := parity_ref;
                    when 3 =>
                        parity_error_out := not parity_ref;
                    when others =>
                        parity_error_out := '1';
                end case;
            end if;
        end if;
        parity_error <= parity_error_out;
    end process;

这里我遇到了一个问题：进程敏感度列表中定义的所有信号都已定义，但根据 GHDL（模拟器），只要 parity_test 变为真，值就会变为未定义： 我做错了什么？

我删除了这里的内容，因为当我换成笔记本电脑时，错误发生了变化：它与机箱开关有关。我仍然不明白为什么。 parity_bit_in_type 是具有范围（0 到 3）的通用 Natural。如果我取出我需要的语句（在这种情况下为 0）并删除 case thingy，一切都会按预期工作。 WebPack ISE 似乎没有抱怨它，所以它开始感觉像是 GHDL 中的一个错误。

GHDL 版本控制：

/Downloads/ghdl-gcc-git » ghdl --version
GHDL 0.34dev (20151126) [Dunoon edition]
 Compiled with GNAT Version: 5.3.0
 mcode code generator
Written by Tristan Gingold.

Copyright (C) 2003 - 2015 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

显示相同行为的最小示例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uart_receiv_parity is
    generic (
        parity_bit_in_type      : Natural range 0 to 3
    );
    port (
        rst                     : in    boolean;
        clk                     : in    STD_LOGIC;
        parity_error            : out   STD_LOGIC  -- Signals that the parity check has failed, is zero if there was none
    );
end entity;

architecture Behavioral of uart_receiv_parity is
begin
    parity_tester : process(clk, rst)
        variable parity_error_out       : STD_LOGIC := '0';
    begin
        if rst then
            parity_error_out    := '0';
        elsif rising_edge(clk) then
            case parity_bit_in_type is
                when 0 =>
                    parity_error_out := '1';
                when 1 =>
                    parity_error_out := '0';
                when 2 =>
                    parity_error_out := '1';
                when 3 =>
                    parity_error_out := '0';
                when others =>
                    parity_error_out := '1';
            end case;
        end if;
        parity_error <= parity_error_out;
    end process;
end Behavioral;

Answer 1

所以，这毕竟是我的错：在测试台中，信号是从两个来源驱动的。因此，“1”导致信号被“1”和“0”驱动，导致“x”。当信号应该是“0”时，输出实际上是零。