【发布时间】：2018-06-24 19:54:04
【问题描述】：
我有一个项目是同步 FIFO 的验证，我已经构建了驱动程序，并且它是成功的。之后，我建立了监视器和记分牌。运行测试台时出现的问题是我无法控制传输到监视器的内容，我从监视器读取的是 DUT 获取的延迟版本（输入数据和输出数据）。所以我总是在记分牌上得到数据缺失匹配。我是初学者，这是我的第一个项目。起初我没有使用时钟模块，后来考虑使用它们，但从我的角度来看，它们只会使监视器和 DUT 的同步变得更加复杂。
我已将监视器时钟块的输入和输出偏差设为 1ps，这与驱动器时钟块相同。我真的很困惑我该怎么做。你能推荐我一些相关的阅读材料吗？
Waveform Viewer Snapshots/notice data actually gets into the fifo memory at 75ps
这是我的驱动程序、监视器、记分牌代码。
/DRIVER/
`include "interface.sv"
`define driv_intf vif.driv.driver_cb
`define mon_intf vif.mon.monitor_cb
class driver;
int no_transactions;
transaction trans;
mailbox gen2drive;
virtual intf vif;
function new(virtual intf vif, mailbox gen2drive);
this.vif = vif;
this.gen2drive = gen2drive;
endfunction
task reset();
$display("------[DRIVER] - RESET TASK - Awaiting Reset--------");
wait(vif.reset);
$display("--------- [DRIVER] Reset Started ---------");
`driv_intf.wr <= 0;
`driv_intf.rd <= 0;
`driv_intf.din <= 0;
`driv_intf.en <= 0;
wait(!vif.reset);
$display("--------- [DRIVER] Reset has ended ---------");
endtask;
task enable();
repeat(5) begin
@(posedge vif.driv.clk)
vif.en <= 1'b1;
end
endtask
task drive();
transaction trans;
gen2drive.get(trans);
@(posedge vif.driv.clk);
if(trans.wr && vif.en) begin
`driv_intf.din <= trans.din;
`driv_intf.rd <= trans.rd;
`driv_intf.wr <= trans.wr;
end
if(trans.rd && vif.en) begin
`driv_intf.din <= trans.din;
`driv_intf.rd <= trans.rd;
`driv_intf.wr <= trans.wr;
end
no_transactions++;
endtask
task main();
forever begin
drive();
end
endtask
endclass/monitor/
`define driv_intf vif.driv.driver_cb
`define mon_intf vif.mon.monitor_cb
class monitor2;
virtual intf vif;
sb scoreboard = new();
function new(virtual intf vif);
this.vif=vif;
endfunction
task mon_push_pop();
begin
logic [31:0] datain;
logic [31:0] dataout;
forever begin
@(posedge vif.driv.clk);
if(vif.rd) begin
dataout = `mon_intf.dout;
scoreboard.compare(dataout);
end
if(vif.wr) begin
datain = `mon_intf.din;
scoreboard.pushItem(datain);
end
end
end
endtask
endclass/SCOREBOARD/
class sb;
mailbox fifo = new(256);
integer size;
static int error = 0;
function new();
this.size = 0;
endfunction
task pushItem(bit [31:0] data);
if(size == 257)
$write("\nTime: %t | [Scoreboard] -- Over Flow has been Detected | Size = %0d",$time,size);
else
fifo.put(data);
$display("\n[SCOREBOARD]--- |Time:%0dns|Entered Value %h\n", $time, data);
size++;
endtask
task compare(bit [31:0] data);
bit [31:0] fifodata = 0;
if(size == 0) begin
$write("\nTime: %0tns | [Scoreboard -- Underflow has been detected | Size = %0d", $time,size);
end
else begin
fifo.get(fifodata);
if(data != fifodata ) begin
$write("\nTime: %0tns | [Scoreboard -- Data Missmatch | Size = %0d, | Actual Data: %0h | Expected Data: %0h",$time,size,data,fifodata);
this.error++;
end
size--;
end
endtask
endclass【问题讨论】：
标签： system-verilog