Verilog 测试台时钟答案

【问题标题】：Verilog Testbench ClockVerilog 测试台时钟
【发布时间】：2014-07-24 04:08:21
【问题描述】：

我已经尝试了多种方法，现在我有点绝望。我试图在我的测试台中制作这个时钟，问题是在模拟中它不起作用或者我的模拟似乎冻结了。我知道它必须是时钟。

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
    end
end
initial begin 
    reset = 0; 
    #15 L = 0; R = 0; H = 0;        
    #20 L = 0; R = 0; H = 1;
    #25 L = 0; R = 1; H = 0;
    #30 L = 0; R = 1; H = 1;
    #35 L = 1; R = 0; H = 0;
    #45 L = 1; R = 0; H = 1;
    #50 L = 1; R = 1; H = 0;
    #55 L = 1; R = 1; H = 1;

    reset = 1; 
    #60 L = 0; R = 0; H = 0;        
    #65 L = 0; R = 0; H = 1;
    #70 L = 0; R = 1; H = 0;
    #75 L = 0; R = 1; H = 1;
    #80 L = 1; R = 0; H = 0;
    #85 L = 1; R = 0; H = 1;
    #90 L = 1; R = 1; H = 0;
    #95 L = 1; R = 1; H = 1;
    $stop ; 
 end

结束模块

【问题讨论】：

标签： verilog hdl

【解决方案1】：

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
 end end

尝试将 clk=0 移到永远循环之上。不是每 #10 切换一次时钟，而是每 #10 单位将时钟重置为 0，然后立即切换一次。我认为这在某些情况下可能仍然有效，但这可能不是您打算做的。

【讨论】：

等一下？我每十个单位将时钟重置为零，我以为我每十个单位切换一次。好的，我会试试的，谢谢！

【解决方案2】：

时钟只需使用

parameter PERIOD = 10; //whatever period you want, it will be based on your timescale

always #PERIOD clk=~clk; //now you create your cyclic clock

//==//

更完整：

module testbench;
timeunit 1ns;
timeprecision 100ps;
initial begin
  $display($time, " << Starting the Simulation >>");
    rstn = 1'b0;
    clk = 0;
    #5 rstn = 1'b1;
end

always #PERIOD clk=~clk;


initial
begin
      $dumpfile("your_choice_of_name.vcd");
      $dumpvars;
end

initial
begin
//whatever you come up
end

endmodule

【讨论】：

我认为将那个时期称为那个时期有点误导，因为你拥有的是那个时期的两倍。
@MattHusz 或者半个周期？

【解决方案3】：

或者干脆这样做..

 initial begin 
        reset = 0; clk = 0;
        #15 L = 0; R = 0; H = 0;        
        #20 L = 0; R = 0; H = 1;
        #25 L = 0; R = 1; H = 0;
        #30 L = 0; R = 1; H = 1;
        #35 L = 1; R = 0; H = 0;
        #45 L = 1; R = 0; H = 1;
        #50 L = 1; R = 1; H = 0;
        #55 L = 1; R = 1; H = 1;

        reset = 1; 
        #60 L = 0; R = 0; H = 0;        
        #65 L = 0; R = 0; H = 1;
        #70 L = 0; R = 1; H = 0;
        #75 L = 0; R = 1; H = 1;
        #80 L = 1; R = 0; H = 0;
        #85 L = 1; R = 0; H = 1;
        #90 L = 1; R = 1; H = 0;
        #95 L = 1; R = 1; H = 1;
        $stop ; 
     end 

always 
   #10 clk = ~clk;

【讨论】：