【发布时间】:2014-06-09 15:20:49
【问题描述】:
我想知道下面代码的行为。有两个always块,一个是组合计算next_state信号,另一个是顺序的,它将执行一些逻辑并确定是否关闭系统。它通过将shutdown_now 信号设置为高电平然后调用state <= next_state 来实现这一点。
我的问题是,如果shutdown_now 信号在state <= next_state 行之前以阻塞方式设置(在时钟周期n 期间)的条件变为真,那么时钟周期n+1 期间的状态是否为SHUTDOWN 或RUNNING?换句话说,由于state 信号通过next_state 确定依赖于它,所以shutdown_now = 1'b1 行是否跨越两个状态机?
enum {IDLE, RUNNING, SHUTDOWN} state, next_state;
logic shutdown_now;
// State machine (combinational)
always_comb begin
case (state)
IDLE: next_state <= RUNNING;
RUNNING: next_state <= shutdown_now ? SHUTDOWN : RUNNING;
SHUTDOWN: next_state <= SHUTDOWN;
default: next_state <= SHUTDOWN;
endcase
end
// Sequential Behavior
always_ff @ (posedge clk) begin
// Some code here
if (/*some condition*/) begin
shutdown_now = 1'b0;
end else begin
shutdown_now = 1'b1;
end
state <= next_state;
end
【问题讨论】:
标签: verilog blocking nonblocking system-verilog