【发布时间】：2019-02-16 08:07:55
【问题描述】：
我正在尝试通过 Quartus 2 实现单周期 MIPS 处理器，但遇到了这些警告。 clk 是我的主模块的输入，它说它不会影响任何输出。我的主模块的输出也卡在 VCC/GND。我想它与clk信号有关。我认为第一个警告的原因是我没有向指令内存写入任何内容，因此您可以忽略它。
那么这些警告的常见原因是什么？有什么想法可以解决吗？
警告 (10858)：instruction_memory.v(7) 处的 Verilog HDL 警告：已使用但从未分配的对象指令。
警告 (13024)：输出引脚卡在 VCC 或 GND
警告 (21074)：设计包含 1 个不驱动逻辑的输入引脚
警告（15610）：没有输出依赖于输入引脚“clk”
我的测试台：
`timescale 1ps/1ps
module mips32_testbench();
wire [31:0] instr;
wire [31:0] R;
wire [31:0] PC;
reg [31:0] counter;
reg clk,clk2;
mips32_single_cycle i0 (.PC_new(PC) ,.instruction(instr) , .result(R) , .clk(clk) );
always
begin
#8 clk = ~clk;
end
always
begin
#24 clk2 = ~clk2;
end
initial
begin
clk = 0;
clk2 = 0;
counter = -1;
$readmemb("registers.mem", i0.MR0.registers);
$readmemb("instructions.tv", i0.IM1.instructions);
$readmemb("datas.mem", i0.ALU1.LW1.DM1.datas);
end
always @(posedge clk2)
begin
//empty
end
always @(negedge clk2)
begin
$display("PC = %5b \n", PC[4:0]);
$display("opcode = %6b, rs = %5b, rt = %5b, rd= %5b, immediate = %16b , address = %26b ,funct = %6b \n",instr[31:26], instr[25:21], instr[20:16], instr[15:11], instr[15:0] , instr[25:0] ,instr[5:0] );
$display("result = %32b \n", i0.result);
counter <= counter + 1 ;
if(PC === 32'b00000000000000000000000000001011)begin
$writememb("regLast.mem",i0.MR1.registers);
$writememb("dataLast.mem",i0.ALU1.LW1.DM1.datas);
$display("%d tests completed. \n",counter);
$finish;
end
end
endmodule
我的顶级模块：
module mips32_single_cycle(PC_new , instruction , result , clk);
input clk;
output [31:0] instruction ;
output [31:0] result;
output [31:0] PC_new;
wire [2:0] select_IJtype, select_Rtype;
wire [31:0] rs , rt , tempr0 , tempr1 ,tempr2;
wire [31:0] R0,R1,R;
wire [31:0] Program_Counter;
wire [4:0] result_register ;
wire [7:0] data_address;
wire data_write_enable;
wire write_enable;
//Unnecessary temp wires
wire t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16,t17,t18,t19,t20,t21;
wire zero;
wire [31:0] tr1,tr2,tr3,tr4;
//PC read
mips_registers MR0 ( tr1 , tr2, 32'b00000000000000000000000000000000, 5'b00000, 5'b00000, 5'b00000, 1'b0, clk ,Program_Counter , 32'b00000000000000000000000000000000 , 1'b0);
//Instruction read
instruction_memory IM1 ( instruction, Program_Counter, clk );
//Creating select signals
control_unit CU1 (select_Rtype, instruction[5:0]);
control_unit_2 CU2 (select_IJtype, instruction[31:26]);
//Pull register source
mips_registers MR1 ( rs , rt, 32'b00000000000000000000000000000000, instruction[25:21], instruction[20:16], instruction[15:11], 1'b0, clk ,tr3 , 32'b00000000000000000000000000000000 , 1'b0);
//Perform the task
alu32_2 ALU1 (data_address, PC_new ,R0 ,select_Rtype ,select_IJtype ,rs ,rt ,instruction , Program_Counter ,clk);
//if this expression is equal to 1 then the instruction we have is sltu:
//select_Rtype[2]select_Rtype[1]'select_Rtype[0]'instruction[0]instruction[31]'instruction[30]'instruction[29]'instruction[28]'instruction[27]'instruction[26]'
not NOT1 (t0 , instruction[31]);
not NOT2 (t1 , instruction[30]);
not NOT3 (t2 , instruction[29]);
not NOT4 (t3 , instruction[28]);
not NOT5 (t4 , instruction[27]);
not NOT6 (t5 , instruction[26]);
not NOT7 (t6 , select_Rtype[1]);
not NOT8 (t7 , select_Rtype[0]);
and AND1 (t8 , t6 , select_Rtype[2]);
and AND2 (t9 , t8 , t7);
and AND3 (t10 , t9 , instruction[0]);
and AND4 (t11 , t10 , t0);
and AND5 (t12 , t11 , t1);
and AND6 (t13 , t12 , t2);
and AND7 (t14 , t13 , t3);
and AND8 (t15 , t14 , t4);
and AND9 (t16 , t15 , t5);
sltu32 SLTU1 (zero ,R1 ,R0);
mux21_32bit M0(result , R0 , R1 , t16);
//If write_enable equals to '0' ,it means that instruction is sw ,j,beq.So write enable signal become 0.
//write_enable = select_IJtype[2]select_IJtype[0]
and AND10 (t19 , select_IJtype[0] , select_IJtype[2] );
not NOT9 (write_enable , t19 );
//R type result ==> rd register
//I type result ==> rt register
//If below expression is equal to 1, it means the instruction is I or J type.
//select_IJtype[0]+select_IJtype[1]+select_IJtype[2]
or OR1 (t17 , select_IJtype[0] , select_IJtype[1]);
or OR2 (t18 , t17 , select_IJtype[2]);
mux21_1bit M1 (result_register[4] , instruction[15] , instruction[20] ,t18);
mux21_1bit M2 (result_register[3] , instruction[14] , instruction[19] ,t18);
mux21_1bit M3 (result_register[2] , instruction[13] , instruction[18] ,t18);
mux21_1bit M4 (result_register[1] , instruction[12] , instruction[17] ,t18);
mux21_1bit M5 (result_register[0] , instruction[11] , instruction[16] ,t18);
//Write back to registers
mips_registers MR2 ( tempr0 , tempr1, result, instruction[25:21], instruction[20:16], result_register, write_enable, clk ,tr4 , PC_new , 1'b1);
//If sw then need to write data_memory
//sw means = select_IJtype[2]select_IJtype[0]select_IJtype[1]'
not NOT10 (t20 , select_IJtype[1]);
and AND11 ( data_write_enable , t20 , t19);
data_memory DM1 (tempr2 , result , data_address , data_write_enable , clk);
endmodule
编辑：我添加了接收时钟信号的模块：
有一个文件包含 32 位寄存器的数据和 PC 计数器。这个模块应该用它做 i/o 操作。
module mips_registers( read_data_1, read_data_2, write_data, read_reg_1, read_reg_2, write_reg, signal_reg_write, clk ,PC_read , PC_write ,PC_write_enable);
output reg[31:0] read_data_1, read_data_2 ,PC_read;
input [31:0] write_data , PC_write;
input [4:0] read_reg_1, read_reg_2, write_reg;
input signal_reg_write, PC_write_enable ,clk;
reg [31:0] registers [32:0];
wire [5:0] rr1,rr2,wr1;
zeroextend_1bit ZE1_1 (rr1 , read_reg_1);
zeroextend_1bit ZE1_2 (rr2 , read_reg_2);
zeroextend_1bit ZE1_3 (wr1 , write_reg);
always@ (posedge clk) begin
if(1 == signal_reg_write)begin
registers[wr1] <= write_data;
end
if(1 == PC_write_enable)begin
registers[6'b100000] <= PC_write;
end
end
always@ (negedge clk) begin
read_data_1 <= registers[rr1];
read_data_2 <= registers[rr2];
PC_read <= registers[6'b100000];
end
endmodule
有一个指令内存 32 x 32。这个模块应该只从内存中输出想要的指令。
module instruction_memory ( read_instruction, PC, clk );
output reg[31:0] read_instruction;
input [31:0] PC;
input clk;
reg [31:0] instructions [31:0];
always@ (negedge clk) begin
read_instruction <= instructions[PC[4:0]];
end
endmodule
这是数据存储模块：
module data_memory ( read_data , write_data, memoryaddress, signal_write_data, clk );
output reg[31:0] read_data;
input [31:0] write_data;
input [7:0] memoryaddress;
input clk , signal_write_data;
reg [31:0] datas [255:0];
always@ (posedge clk) begin
if(1 == signal_write_data)begin
datas[memoryaddress] <= write_data;
end
end
always@ (negedge clk) begin
read_data <= datas[memoryaddress];
end
endmodule
这是我的 ALU。 loadword,storeword 和 nextPC 在内部使用内存模块，这就是它们采用时钟信号的原因：
module alu32_2 (data_address ,PC_new , R ,select_Rtype ,select_IJtype ,rs ,rt ,instr ,PC ,clk);
input [31:0] rs,rt;
input [31:0] instr;
input [2:0] select_IJtype, select_Rtype;
input [31:0] PC;
input clk;
output [31:0] R , PC_new;
output [7:0] data_address;
wire [31:0] I0,I1,I2,I3,I4,I5,I6,I7;
wire ZANDI,ZORI,ZADDIU;
wire OADDIU;
wire CADDIU;
wire [31:0] EXT;
wire overflow;
wire zero;
zeroextendimm EXT1 (EXT , instr[15:0] );
Rtype_alu_controller ROC1 (overflow , zero ,I0 ,select_Rtype ,rs ,rt ,instr[10:5]);
and32 AND1 (ZANDI,I1,rs,EXT);
or32 OR1 (ZORI,I2,rs,EXT);
add32 ADD1 (OADDIU,ZADDIU,CADDIU,I3,rs,EXT,1'b0);
loadword LW1 (I4,instr[20:16],rs,instr[15:0],clk);
storeword SW1 (I5,data_address,instr[20:16],rs,instr[15:0],clk);
beq BEQ1 (I6,PC,rs,rt,instr[15:0]);
j J1 (I7,PC,instr[25:0]);
mux81_32bit M1 (R,I0,I1,I2,I3,I4,I5,I6,I7,select_IJtype);
nextPC NPC (PC_new ,I6 , I7 , PC ,select_IJtype ,clk);
endmodule
【问题讨论】：
-
要么你没有用相应的 $readmem 编译你的测试台代码，要么文件没有初始化所有的内存。另外，如果您从不使用
clk输入，它有什么意义？ -
我没有得到您关注的重点。我正在使用
clk输入，但它说它不驱动任何逻辑，这是这里的问题。编译器没有给出任何错误但给出我在上面描述的警告。文件初始化内存（我检查了。）但是带有clk输入的模块无法正常工作。我在时钟使用方面做错了吗？ -
未使用的 clk 让我认为您可能有逻辑问题或未完成的模块。我不知道是真是假，只是一个危险信号。
-
如果有一个未完成的模块，那么不会有编译错误吗？如果你愿意，如果这些模块不足以澄清问题，我可以上传我的洞项目。 @Serge
-
您的约束中可能有一个错误命名的引脚。检查您的约束文件是否有名为“clk”的引脚。