如何连接 VHDL 代码的组件答案

【问题标题】：How to connect components of VHDL code如何连接 VHDL 代码的组件
【发布时间】：2013-05-23 22:50:49
【问题描述】：

我有 2 个组件在仿真中单独工作，但现在我对如何在我的板上实现设计感到困惑。我有一种设计是二进制到 7 段显示器，另一种是计数器，以秒为单位向上计数。

如何将这两者连接起来一起工作以在 basys2 板上显示值？

计时器代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clock IS
port(reset,clk,start,stop:in std_logic;
min,sec:out integer);
end clock;
architecture behaviour of clock is
begin
process(reset,clk,start,stop)
variable tempmin,tempsec:integer:=0;
begin
if(reset='1')then
tempmin:=0;
tempsec:=0;
elsif(stop='1')then
min<=tempmin;
sec<=tempsec;
elsif(start='1')then
if(rising_edge(clk))then
tempsec:=tempsec+1;
if(tempsec=60)then
tempsec:=0;
tempmin:=tempmin+1;
if(tempmin=10)then
tempmin:=0;
end if;
end if;
end if;
end if;
min<=tempmin;
sec<=tempsec;
end process;
end behaviour;

二进制转七段代码

architecture Behavioral of SevenSegment is
begin 
process (seg_value)
begin  
if (seg_value = "0000") then
seg <= "0000001";
an <= "1100";
elsif (seg_value = "0001") then
seg <= "1001111";
an <= "1100";
elsif (seg_value = "0010") then
seg <= "0010010";
an <= "1100";
elsif (seg_value = "0011") then
seg <= "0000110";
an <= "1100";
elsif (seg_value = "0100") then
seg <= "1001100";
an <= "1100";
elsif (seg_value = "0101") then
seg <= "0100100";
an <= "1100";
elsif (seg_value = "0110") then
seg <= "0100000";
an <= "1100";
elsif (seg_value = "0111") then
seg <= "0001111";
an <= "1100";
elsif (seg_value = "1000") then
seg <= "0000000";
an <= "1100";
elsif (seg_value = "1001") then
seg <= "0000100";
an <= "1100";
end if;
end process;
end Behavioral;

【问题讨论】：

创建顶级实体；在其中实例化时钟模块；为您的 7 段代码创建一个实体；在顶层模块中实例化它。

标签： counter vhdl

【解决方案1】：

在您的 VHDL 教科书中查找组件实例化（或实体实例化）的语法。 Emacs VHDL 模式和 Sigasi 提供了强大的模板，因此您不必输入太多代码：http://www.sigasi.com/screencast/entity-instantiation

【讨论】：