【问题标题】:Python: Code for VHDL Code GeneratorPython:VHDL 代码生成器的代码
【发布时间】:2011-02-11 08:47:12
【问题描述】:

我正在尝试用 VHDL 语言制作一个 ROM,我正在使用我在 http://www.edaboard.com/thread38052.html 上找到的这个模板:

library ieee;
use ieee.std_logic_1164.all;

entity ROM is
port ( address : in std_logic_vector(3 downto 0);
     data : out std_logic_vector(7 downto 0) );
end entity ROM;

architecture behavioral of ROM is
type mem is array ( 0 to 2**4 - 1) of std_logic_vector(7 downto 0);
constant my_Rom : mem := (
0  => "00000000",
1  => "00000001",
2  => "00000010",
3  => "00000011",
4  => "00000100",
5  => "11110000",
6  => "11110000",
7  => "11110000",
8  => "11110000",
9  => "11110000",
10 => "11110000",
11 => "11110000",
12 => "11110000",
13 => "11110000",
14 => "11110000",
15 => "11110000");
begin
process (address)
begin
 case address is
   when "0000" => data <= my_rom(0);
   when "0001" => data <= my_rom(1);
   when "0010" => data <= my_rom(2);
   when "0011" => data <= my_rom(3);
   when "0100" => data <= my_rom(4);
   when "0101" => data <= my_rom(5);
   when "0110" => data <= my_rom(6);
   when "0111" => data <= my_rom(7);
   when "1000" => data <= my_rom(8);
   when "1001" => data <= my_rom(9);
   when "1010" => data <= my_rom(10);
   when "1011" => data <= my_rom(11);
   when "1100" => data <= my_rom(12);
   when "1101" => data <= my_rom(13);
   when "1110" => data <= my_rom(14);
   when "1111" => data <= my_rom(15);
   when others => data <= "00000000";
 end case;
  end process;
  end architecture behavioral;

好吧,问题是我想输入我的 ROM 2000 值。所以我想知道如何使用python制作下一个:

想象一下,您在 .txt 文件中有以下格式的数据:

0  45
1  56
2  78
3  98

所以程序会对数据执行此操作:

0 => "00101101"
1 => "00111000"
2 => "01001110"
3 => "01100010"

这些值 "00101101","00111000","01001110","01100010" 是 45,56,78 y 89 的二进制表示的各自值。 所以,你明白了……

有个小细节,需要指定表示的位数: 如果你不这样做,你可以得到这个:

0 => "101101"
1 => "111000"
2 => "1001110"
3 => "1100010"

非常感谢所有可能的代码片段来完成这个程序

【问题讨论】:

  • +1 表示不想长期做事!
  • 2000 个值太多了!!! :)

标签: python code-generation vhdl rom


【解决方案1】:

作为其他答案的替代方案,将您的 ROM 存储为 naturals 或 integers(视情况而定)。那么你的常量可以是以下形式:

0 => 45,
1 => 56, ...

等等

如果您已经所有值,您可以将它们全部放在一个大的逗号分隔符系列中,而无需进行n =&gt; 位置映射。

(45, 56, 78, 98,....)

此外,如果您将地址输入为数字类型(unsignednatural,您可以随意),您可以将地址解码简化为

data <= my_rom(address);

data <= my_rom(to_integer(address));

【讨论】:

    【解决方案2】:

    这是另一种方法;在 MyHDL 中使用 toVHDL 转换器。您可以使用任意 Python 表达式来初始化一个元组。

    这是 MyHDL 描述:

    from myhdl import *
    
    def VhdlRomGen(addr, data):
    
        # Create the ROM container
        rom = [Signal(intbv(0)[8:]) for ii in range(2**4)]
    
        # Initialize ROM, any value, any complex python can
        # be in this initialization code.
        for ii in xrange(len(rom)):
            rom[ii] = ii
    
        rom = tuple(rom)
    
        @always_comb
        def rtl_rom():
            data.next = rom[int(addr)]
    
    
        return rtl_rom
    
    if __name__ == "__main__":
        addr = Signal(intbv(0)[4:])
        data = Signal(intbv(0)[8:])
    
        toVHDL(VhdlRomGen, addr, data)
    

    这是转换后的 VHDL:

    -- Generated by MyHDL 0.7
    -- Date: Sat May 21 15:39:27 2011
    
    
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use std.textio.all;
    
    use work.pck_myhdl_07.all;
    
    entity VhdlRomGen is
            port (
                addr: in unsigned(3 downto 0);
                data: out unsigned(7 downto 0)
            );
    end entity VhdlRomGen;
    
    
    architecture MyHDL of VhdlRomGen is
    begin
    
    VHDLROMGEN_RTL_ROM: process (addr) is
    begin
        case to_integer(addr) is
            when 0 => data <= "00000000";
            when 1 => data <= "00000001";
            when 2 => data <= "00000010";
            when 3 => data <= "00000011";
            when 4 => data <= "00000100";
            when 5 => data <= "00000101";
            when 6 => data <= "00000110";
            when 7 => data <= "00000111";
            when 8 => data <= "00001000";
            when 9 => data <= "00001001";
            when 10 => data <= "00001010";
            when 11 => data <= "00001011";
            when 12 => data <= "00001100";
            when 13 => data <= "00001101";
            when 14 => data <= "00001110";
            when others => data <= "00001111";
        end case;
    end process VHDLROMGEN_RTL_ROM;
    end architecture MyHDL;
    

    【讨论】:

    • @FakeName 对于 Python 3.x 需要将 xrange 替换为 range,应该适用于 2.7。
    【解决方案3】:
    for line in open('your_file.txt'):
        s = line.strip().split("  ") # two spaces are for split
        p = '{} => "{:0{min_bits}b}"'.format(s[0], int(s[1]), min_bits=10)
        print p
    

    【讨论】:

      【解决方案4】:

      试试这个:

      bit_count = 8
      format_template = '{{0}} => "{{1:0{0}b}}"'.format(bit_count)
      with open(r"input_file.txt") as input_file:
          for line in input_file:
              data = map(int, line.split())
              print format_template.format(*data)
      

      【讨论】:

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