【发布时间】：2013-11-11 05:04:28
【问题描述】：
我正在尝试使用 VHDL 创建一个超前进位加法器/减法器单元作为 ALU 的一部分。 与传统的加法器不同，该单元必须同时识别 32 位未打包数据和 16 位打包数据并相应地处理它们。所以，如果我选择添加两个 32 位解压缩量，它应该会给我一个 32 位解压缩结果。但是，如果我想添加四个 16 位压缩量，它应该给我两个 16 位压缩结果。
即。
32_bit_A + 32_bit_B = 32_bit_A+B
16_bit_A + 16_bit_B, 16_bit_C + 16_bit_D = 16_bit_A+B, 16_bit_C+D
我尝试使用 MODE 位来实现这样的事情，该位将确定我是使用打包数据还是解包数据，但是，我的 VHDL 编译器一直告诉我它需要 generate 关键字，在我相当困惑的其他错误中。 我应该注意，这种设计可以完美地编译并适用于解压数据，也就是说，没有条件语句以及 cla4 和 cla5。我希望能解释一下我做错了什么。谢谢
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity thirty_two_bit_cla is
port
(
A : in std_logic_vector(31 downto 0); -- 32-bit augend
B : in std_logic_vector(31 downto 0); -- 32-bit addend
SUM : out std_logic_vector(31 downto 0); -- 32-bit sum
CARRY_OUT : out std_logic; -- carry out
CARRY_IN : in std_logic; -- carry in
P_G : out std_logic; -- group propagate
G_G : out std_logic; -- group generate
MODE : in std_logic -- 16 or 32-bit addition (0 or 1 respectively)
);
end thirty_two_bit_cla;
architecture structural of thirty_two_bit_cla is
signal G : std_logic_vector(1 downto 0); --generate signals
signal P : std_logic_vector(1 downto 0); --propagate signals
signal C : std_logic_vector(2 downto 0); --carry signals
begin
--Treat data as 32-bit unpacked
if(MODE = '1') then
sixteen_bit_cla0: entity sixteen_bit_cla port map(A=>A(15 downto 0),
B=>B(15 downto 0),
SUM=>SUM(15 downto 0),
CARRY_IN=>C(0),
P_G => P(0),
G_G => G(0));
sixteen_bit_cla1: entity sixteen_bit_cla port map(A=>A(31 downto 16),
B=>B(31 downto 16),
SUM=>SUM(31 downto 16),
CARRY_IN=>C(1),
P_G => P(1),
G_G => G(1));
C(0) <= CARRY_IN;
C(1) <= G(0) or (P(0) and C(0));
C(2) <= G(1) or (P(1) and C(1));
CARRY_OUT <= C(2);
G_G<=C(2);
P_G <= P(0) and P(1);
--Treat data as 16-bit packed
elsif (MODE = '0') then
sixteen_bit_cla4: entity sixteen_bit_cla port map(A=>A(15 downto 0),
B=>B(15 downto 0),
SUM=>SUM(15 downto 0),
CARRY_IN=>CARRY_IN);
sixteen_bit_cla5: entity sixteen_bit_cla port map(A=>A(31 downto 16),
B=>B(31 downto 16),
SUM=>SUM(31 downto 16),
CARRY_IN=>CARRY_IN);
end if;
end structural;
错误：
# Compile Entity "thirty_two_bit_cla"
# Compile Architecture "structural" of Entity "thirty_two_bit_cla"
# Error: COMP96_0329: 32 bit cla.vhd : (26, 5): Generate statement must have a label.
# Error: COMP96_0019: 32 bit cla.vhd : (26, 20): Keyword 'generate' expected.
# Error: COMP96_0019: 32 bit cla.vhd : (52, 2): Keyword 'end' expected.
# Error: COMP96_0016: 32 bit cla.vhd : (52, 8): Design unit declaration expected.
# Compile Entity "sixteen_bit_cla"
# Error: COMP96_0019: 32 bit cla.vhd : (53, 43): Keyword 'is' expected.
# Error: COMP96_0015: 32 bit cla.vhd : (53, 48): '(' expected.
# Error: COMP96_0028: 32 bit cla.vhd : (53, 48): Identifier or keyword expected.
# Error: COMP96_0015: 32 bit cla.vhd : (53, 48): ';' expected.
# Error: COMP96_0019: 32 bit cla.vhd : (53, 51): Keyword 'end' expected.
# Error: COMP96_0015: 32 bit cla.vhd : (53, 51): ';' expected.
# Error: COMP96_0016: 32 bit cla.vhd : (53, 52): Design unit declaration expected.
# Compile Entity "sixteen_bit_cla"
# Error: COMP96_0019: 32 bit cla.vhd : (58, 45): Keyword 'is' expected.
# Error: COMP96_0015: 32 bit cla.vhd : (58, 50): '(' expected.
# Error: COMP96_0028: 32 bit cla.vhd : (58, 50): Identifier or keyword expected.
# Error: COMP96_0015: 32 bit cla.vhd : (58, 50): ';' expected.
# Error: COMP96_0019: 32 bit cla.vhd : (58, 53): Keyword 'end' expected.
# Error: COMP96_0015: 32 bit cla.vhd : (58, 53): ';' expected.
# Error: COMP96_0016: 32 bit cla.vhd : (58, 54): Design unit declaration expected.
# Compile failure 18 Errors 0 Warnings Analysis time : 16.0 [ms]
# ULM: Warning: ULM_0021 Architecture `structural' of entity `register_file.thirty_two_bit_cla' is not up-to-date.
【问题讨论】：
标签： compiler-errors vhdl hdl alu