无法运行后期合成 vivado

Question

我正在尝试运行综合后功能仿真。当我运行行为模拟代码时，我得到了输出并且一切运行良好。但是当我运行后期合成时，我收到以下错误：

错误：[VRFC 10-3146] 绑定实体“rippleadder_nbit”没有通用“n”[C:/Users/gauta/Assignment4/Assignment4.srcs/sim_1/new/tb_ripplenbit.vhd:41]

谁能解释一下我需要做什么。我是 Vivado 的新手，对如何使用它很困惑

我的 Rippleadder 代码是：

entity rippleadder_nbit is
generic(n: natural);
    Port ( cin_ra : in STD_LOGIC;
           a : in STD_LOGIC_VECTOR (n-1 downto 0);
           b : in STD_LOGIC_VECTOR (n-1 downto 0);
           s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
           cout_ra : out STD_LOGIC);
end rippleadder_nbit;

architecture Behavioral of rippleadder_nbit is
component fulladder port(
                            x_fa : in STD_LOGIC;
                            y_fa : in STD_LOGIC;
                            z_fa : in STD_LOGIC;
                            s_fa : out STD_LOGIC;
                            c_fa : out STD_LOGIC);
end component;

signal r: std_logic_vector(n downto 0);                            

begin
 r(0) <= cin_ra;
 cout_ra <= r(n);
 FA: for i in 0 to n-1 generate
     FA_i : fulladder port map(r(i),a(i),b(i),s_ra(i),r(i+1));
 end generate;

end Behavioral;

我的测试台如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tb_ripplenbit is
 -- Port ( s: std_logic_vector(2 downto 0);
       -- cout: std_logic);
end tb_ripplenbit;

architecture Behavioral of tb_ripplenbit is 
component rippleadder_nbit
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
           a : in STD_LOGIC_VECTOR (n-1 downto 0);
           b : in STD_LOGIC_VECTOR (n-1 downto 0);
           s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
           cout_ra : out STD_LOGIC);
end component;
signal a,b,sin : STD_LOGIC_VECTOR (3 downto 0);
signal cin,carry_out : std_logic;
constant c : integer :=4;

begin
a <=  "0000", "0001" after 50 ns, "0101" after 100ns;
b <=  "0010", "0011" after 50 ns, "1010" after 100 ns;
cin <= '1', '0' after 50 ns;

UUT1 : rippleadder_nbit generic map(n => c) port map(cin_ra => cin,a=>a,b=>b,s_ra=>sin,cout_ra =>carry_out);

end Behavioral;

Answer 1

在综合后/实施后，泛型（常量）被删除，这些泛型的用法被替换为常量值

在测试台中，您有实例 w.r.t 到行为模型（涉及泛型），因此相同的测试台不适用于合成后/实施后模拟

来源：赛灵思论坛