在 Verilog 中推断真正的双端口 RAM（Xilinx 和 Intel 兼容）

Question

我尝试编写自己的真正双端口内存模块，希望它能推断为 BRAM：

module dp_async_ram (clk, rst, rd0, rd1, wr0, wr1, in1, in0, out1,out0, addr0, addr1);
  parameter DEPTH = 16;
  parameter WIDTH = 8;
  parameter ADDR = 4;

  input clk, rst;
  input rd0, rd1;
  input wr0, wr1;
  input [WIDTH-1:0] in0, in1;
  input [ADDR-1:0] addr0, addr1;

  output [WIDTH-1:0] out0, out1;

  //Define Memory
  logic [WIDTH-1:0] mem [0:DEPTH-1];
  logic [WIDTH-1:0] data0, data1;

  //Write Logic
  always_ff @ (posedge clk) begin
      if (wr0 && ~rd0)
        mem[addr0] <= in0;
      if (wr1 && ~rd1)
        mem[addr1] <= in1;
      if (rd0 && ~wr0)
        data0 <= mem[addr0];
      if (rd1 && ~wr1)
        data1 <= mem[addr1];
  end

  //Read Logic
  assign out0 = (rd0 && (!wr0))? data0: {WIDTH{1'bz}}; //High Impedance Mode here
  assign out1 = (rd0 && (!wr0))? data1: {WIDTH{1'bz}};


endmodule // dp_async_ram

在 Vivado 中运行综合后，报告中显示以下内容：

 WARNING: [Synth 8-4767] Trying to implement RAM 'mem_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
    1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process. 
    2: Unable to determine number of words or word size in RAM. 
    3: No valid read/write found for RAM. 
RAM "mem_reg" dissolved into registers

数字 1 最让我印象深刻，因为这意味着无法编写便携式真正的双端口 BRAM。我想知道我是否错了，或者我是否应该只使用 ip 生成。谢谢

Answer 1

我不认为#1 意味着你不能进行多次写入——只是你不能从同一个进程中进行。尝试将它们分开：

always_ff @ (posedge clk) begin
    if (wr0 && ~rd0)
        mem[addr0] <= in0;
    if (rd0 && ~wr0)
        data0 <= mem[addr0];
end
always_ff @ (posedge clk) begin
    if (wr1 && ~rd1)
        mem[addr1] <= in1;
    if (rd1 && ~wr1)
        data1 <= mem[addr1];
end

有关如何在 Vivado 中推断事物的更多信息，请查看“UG901 Vivado 综合”文档。对于 TDP BRAM，请查看“RAM HDL 编码技术”。

或者，如果您不介意被赛灵思锁定，您可以使用xpm_memory_tdpram 模块。