警告：(vsim-3015) [PCDPC] - 端口大小 (8) 与连接大小 (7) 不匹配

Question

这些是我收到的警告：

警告：(vsim-3015) [PCDPC] - 端口大小 (8) 与端口“wrdata”的连接大小 (7) 不匹配。端口定义位于：design.sv(2)。
时间：0 ns 迭代：0 实例：/tb/DUT 文件：testbench.sv 行：15

警告：(vsim-3015) [PCDPC] - 端口大小 (8) 与端口“rddata”的连接大小 (7) 不匹配。端口定义位于：design.sv(2)。
时间：0 ns 迭代：0 实例：/tb/DUT 文件：testbench.sv 行：15

这是导致这些警告的代码：

module fifo (
        clk,
        rst,
        full,
        error,
        empty,
        wr_en,
        rd_en,
        wrdata,
        rddata
);
    parameter WIDTH = 8;
    parameter DEPTH = 16;
    parameter PTR_WIDTH = 4;
    input clk, rst, wr_en, rd_en;
    input [WIDTH-1:0] wrdata;
    output reg [WIDTH-1:0] rddata;
    output reg full, empty, error;

    reg [WIDTH-1:0] mem[DEPTH-1:0];
    reg [PTR_WIDTH-1:0] rd_ptr, wr_ptr;
    reg wr_toggle, rd_toggle;
    integer i;

    always @(posedge clk or rst) begin
        if (rst) begin
            rddata = 0;
            full = 0;
            empty = 1;
            error = 0;
            wr_toggle = 0;
            rd_toggle = 0;
            rd_ptr = 0;
            wr_ptr = 0;
            for (i = 0; i < DEPTH - 1; i = i + 1) mem[i] = 0;
        end else begin
            error = 0;
            if (wr_en == 1) begin
                if (full == 1) begin
                    $display("ERROR:WRITING INTO FULL FIFO");
                    error = 1;
                end else begin
                    mem[wr_ptr] = wrdata;
                    if (wr_ptr == DEPTH - 1) begin
                        wr_toggle = ~wr_toggle;
                        wr_ptr = 0;
                    end else begin
                        wr_ptr = wr_ptr + 1;
                    end
                end
            end
            if (rd_en == 1) begin
                if (empty == 1) begin
                    $display("ERROR:READING FROM FULL FIFO");
                    error = 1;
                end else begin
                    rddata = mem[rd_ptr];
                    if (rd_ptr == DEPTH - 1) begin
                        rd_toggle = ~rd_toggle;
                        rd_ptr = 0;
                    end else begin
                        rd_ptr = rd_ptr + 1;
                    end
                end
            end
        end
    end

    always @(wr_ptr or rd_ptr) begin
        full  = 0;
        empty = 0;
        if (wr_ptr == rd_ptr && wr_toggle == rd_toggle) begin
            empty = 1;
            full  = 0;
        end
        if (wr_ptr == rd_ptr && wr_toggle != rd_toggle) begin
            full  = 1;
            empty = 0;
        end
    end

endmodule

这是我的测试平台代码：

module tb;
    parameter WIDTH = 8;
    parameter DEPTH = 16;
    parameter PTR_WIDTH = 4;
    reg clk, rst, wr_en, rd_en;
    reg  [WIDTH-1] wrdata;
    wire [WIDTH-1] rddata;
    wire full, empty, error;
    wire [WIDTH-1:0] mem[DEPTH-1:0];
    wire [PTR_WIDTH-1:0] rd_ptr, wr_ptr;
    wire wr_toggle, rd_toggle;
    integer i;

    fifo DUT (
            clk,
            rst,
            full,
            error,
            empty,
            wr_en,
            rd_en,
            wrdata,
            rddata
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        rst = 1;
        repeat (2) @(posedge clk) rst = 0;
        for (i = 0; i < DEPTH; i = i + 1) begin
            @(posedge clk);
            wr_en  = 1;
            wrdata = $urandom_range(100, 200);
        end
        @(posedge clk);
        wr_en  = 0;
        wrdata = 0;
        for (i = 0; i < DEPTH; i = i + 1) begin
            @(posedge clk);
            rd_en = 1;
        end
        @(posedge clk);
        rd_en = 0;
        #100;
        $finish;
    end

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
    end

endmodule

截图：

Answer 1

在测试台中，更改：

      reg [WIDTH-1] wrdata;
      wire [WIDTH-1] rddata;

到：

      reg [WIDTH-1:0] wrdata;
      wire [WIDTH-1:0] rddata;

这消除了对我的警告。

当我在 Cadence 模拟器上运行您的代码时，我收到一条更有意义的消息，这是一个错误，而不是警告：

          reg [WIDTH-1] wrdata;
                      |
xmvlog: *E,SVPKSN : The single-bound form of a range is only allowed for array (i.e., unpacked) dimensions.

由于您使用的是edaplayground，因此最好在多个模拟器上运行您的代码。有时您会收到更具体的消息。

这里是对错误更详细的解释（使用nchelp 命令）：

xmvlog/SVPKSN =
    By SystemVerilog language rules a range such as [SIZE] (meaning [0:SIZE-1])
    is only allowed for array dimensions (that is, "unpacked array" dimensions).
    For example, this form of a range is not permitted for vector dimensions
    (that is, "packed array" dimensions in SystemVerilog terminology).