Verilog 未完全读取文件答案

【问题标题】：Verilog not fully reading the fileVerilog 未完全读取文件
【发布时间】：2021-03-11 18:53:57
【问题描述】：

我正在尝试从文件中读取输入，但它没有完全读取文件。如果有 100 个条目，它只会读取 99。这是文件和代码。任何帮助，将不胜感激。我怎么知道？它基本上是hit_count 和miss_count 的总和应该是文件中输入的总数，也就是缺少1。

module cache_memory_direct_mapped(input clk,
                        input reset,
                        input [3:0]read_addr,
                        output reg hit,
                        output reg miss,
                        output reg [7:0]hit_count,
                        output reg [7:0]miss_count);
reg [1:0]c1[3:0];
 initial 
begin
 hit_count =8'h00; 
 miss_count = 8'h00;
end 
            

always @(posedge clk, posedge reset)                        
 begin
   if(reset)
      begin
       c1[0] <= 2'hx;
       c1[1] <= 2'hx;
       c1[2] <= 2'hx;
       c1[3] <= 2'hx;
      end   
    else  
  begin
   if(read_addr[3:2] == c1[0] || read_addr[3:2] == c1[1] || read_addr[3:2] == c1[2] || read_addr[3:2]     
  == c1[3])
   begin
    hit <= 1;
     hit_count <= hit_count + 1;
     miss <= 0;
   end
  else
  begin
    hit <= 0;
    miss <= 1;
    miss_count <= miss_count + 1;
     if(read_addr[1:0] == 2'b0 )
      c1[0] <= read_addr[3:2];
  else if(read_addr[1:0] == 2'b1 )
      c1[1] <= read_addr[3:2];  
  else if(read_addr[1:0] == 2'b10 )
      c1[2] <= read_addr[3:2];        
  else if(read_addr[1:0] == 2'b11 )
      c1[3] <= read_addr[3:2];  
end
end
end
endmodule

module Tb_direct_mapped;

// Inputs
reg clk;
reg reset;
reg [3:0] read_addr;

// Outputs
wire hit;
wire miss;
wire [7:0]hit_count;
wire [7:0]miss_count;

integer data_file ; // file handler
integer scan_file ; // file handler
reg [4:0]captured_data;

// Instantiate the Unit Under Test (UUT)
cache_memory_direct_mapped uut (
    .clk(clk), 
    .reset(reset), 
    .read_addr(read_addr), 
    .hit(hit), 
    .miss(miss),
    .hit_count(hit_count),
    .miss_count(miss_count)
);

initial begin
    // Initialize Inputs
    clk = 0;
    reset = 0;
    data_file = $fopen("data_file.txt", "r");
end

always
#10 clk= ~clk;
always @(posedge clk) begin
scan_file = $fscanf(data_file, "%h\n", captured_data);
 if (!$feof(data_file)) begin
 read_addr <= captured_data;
 //$strobe(hit_count);
 end
 else begin
 //$display("The total hit counts are:");
  $display(hit_count);
  $display(miss_count);
  $finish;
   end
  end        
  endmodule

这是文件：

【问题讨论】：

标签： verilog

【解决方案1】：

在读取文件的每一行之前检查 EOF：

   always @(posedge clk) begin
      if (!$feof(data_file)) begin
         scan_file = $fscanf(data_file, "%h\n", captured_data);
         read_addr <= captured_data;
         //$strobe(hit_count);
      end
      else begin
         //$display("The total hit counts are:");
         $display(hit_count);
         $display(miss_count);
         $finish;
      end
   end

【讨论】：